Interconnect Design Engineer

Job Title

Interconnect Design Engineer

Role Summary

Design and implement interconnect and uncore IP (TileLink interconnects, cache controllers, protocol bridges) as configurable RTL generators using Chisel/FIRRTL. Work with CPU and infrastructure teams to deliver high-performance, configurable IP for SoC designs.

This is a staff-level engineering role focused on producing production-quality hardware generators, improving coherence/performance, and integrating designs into automated build, verification, and documentation flows.

Experience Level

Senior (staff-level). Years of experience not specified.

Responsibilities

Primary responsibilities include architecture, design, verification integration, and documentation for interconnect and uncore IP.

• Architect, design, and implement TileLink interconnects, cache controllers, protocol bridges, and other infrastructure as RTL generators in Chisel.
• Implement RTL generators that self-configure to optimally connect system elements.
• Improve designs for higher performance and more efficient multi-core and multi-system coherence.
• Design extensive configurability as a first-class concern.
• Integrate new content into the Chisel/FIRRTL framework and contribute framework improvements to automate documentation, verification testbenches, and tests.
• Perform initial sandbox verification and collaborate with the design verification team to create and execute verification plans.
• Create and maintain technical documentation and participate in collaborative design reviews and knowledge sharing.

Requirements

Must-have technical skills and capabilities required for the role; a short "nice-to-have" list follows.

• Knowledge of cache and cache coherency architectures and concepts.
• Experience with NoC or other interconnect fabrics.
• Familiarity with industry-standard bus protocols (AXI, AHB, APB, CHI).
• Ability to architect solutions that connect disparate bus fabrics and protocol domains.
• Strong software engineering background, including familiarity with object-oriented and functional programming, templated metaprogramming, compiler infrastructures (DSLs), data modeling for IRs, and test-driven development.
• Proficiency in RTL design using Verilog, SystemVerilog, or VHDL.
• Attention to detail, focus on high-quality design, and ability to work collaboratively in team settings.

Nice-to-have

• Experience with Scala/Chisel, Bluespec, or other hardware DSLs for configurable hardware generation.
• Knowledge of the RISC-V architecture.
• Experience with Git/GitHub, Jira, and Confluence.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline, or equivalent practical experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.