Engineer / Staff / Sr. Staff Engineer - CPU Verification (RAS)
SiFiveJob Title
Engineer / Staff / Sr. Staff Engineer - CPU Verification (RAS)
Role Summary
Work on CPU IP verification with emphasis on reliability, availability, and serviceability (RAS). The role covers development and maintenance of SystemVerilog/UVM testbenches, test plan implementation, automated regressions, and cross-team debugging with RTL designers.
This posting hires across multiple seniority levels; exact scope and ownership will be matched to experience and demonstrated capability.
Experience Level
Multiple levels: Engineer through Sr. Staff (early-career to senior). Hiring ranges from candidates with ~1+ years of verification experience up to senior engineers with broad technical ownership; specific leveling will be determined during evaluation.
Responsibilities
Primary responsibilities include building and running verification environments, producing tests, and driving bug resolution with designers.
- Design, maintain, and extend block- and subsystem-level testbenches using SystemVerilog and UVM.
- Extract verification requirements from architecture specs and contribute to test plans and reviews.
- Develop directed and constrained-random tests to meet functional and coverage goals.
- Debug simulation failures, perform root-cause analysis, and collaborate with RTL engineers to resolve issues.
- Maintain and optimize automated regression infrastructure and flows.
Requirements
Must-have technical skills and experience for successful candidates.
Must-have
- Strong understanding of advanced computer architecture: pipelines, memory hierarchies, and caches.
- Proficient in SystemVerilog and Universal Verification Methodology (UVM).
- Solid grasp of hardware verification concepts, including constrained-random stimulus and coverage-driven verification.
- Experience debugging simulations and analyzing RTL/verification interactions.
- Familiarity with scripting for automation (Python, Perl, Bash).
Nice-to-have
- Experience with RAS architecture and verification techniques (ECC testing, parity, data poisoning, fault injection).
- Knowledge of the RISC-V ISA and custom extensions.
Education Requirements
Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field is specified; the posting notes hiring at levels where ~1+ years of experience is typical with these degrees.
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
