Staff RTL Design Engineer - CPU Midcore

Job Title

Staff RTL Design Engineer - CPU Midcore

Role Summary

Design microarchitecture and RTL for high-performance RISC-V CPU cores. Work within a CPU core team to implement features in Chisel and traditional HDLs, and collaborate with verification, physical implementation, and performance teams to deliver production-quality CPU IP.

Experience Level

Senior — typically 5+ years of RTL or CPU microarchitecture design experience.

Responsibilities

Key responsibilities include:

• Architect, design and implement new features, performance improvements, and ISA extensions using Chisel.
• Integrate designs into the Chisel/FIRRTL framework and improve tooling for automatic configuration, documentation, verification, and software packaging.
• Perform initial sandbox verification and coordinate with verification teams to develop and execute verification plans.
• Collaborate with physical implementation engineers to meet frequency, area, and power targets.
• Work with performance modeling teams for exploration and optimization.
• Develop microarchitecture specifications and maintain clear documentation.

Requirements

Must-have:

• 5+ years of design experience.
• Professional experience with CPU RTL design.
• Proficiency in Verilog, SystemVerilog, or VHDL.
• Strong software engineering skills, including functional programming, templated metaprogramming, compiler or DSL infrastructure, data modeling, and test-driven development.
• Attention to detail and commitment to high-quality design.
• Ability to work effectively in engineering teams.
• Successful background and reference checks; proof of right to work in the United Kingdom.

Nice-to-have:

• Experience with Scala/Chisel, Bluespec, or other hardware DSLs.
• Knowledge of RISC-V architecture.
• Expertise in CPU subsystems (decode, register renaming, reorder buffer, scheduling, vector units, load-store unit).
• Familiarity with verification methodologies, UVM, and coverage-driven verification.
• Experience with Git/GitHub, Jira, and Confluence.

Education Requirements

Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field, or equivalent practical experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.