Staff RTL Design Engineer - CPU LS/PF/MMU
SiFiveJob Title
Staff RTL Design Engineer - CPU LS/PF/MMU
Role Summary
Design and implement microarchitecture and RTL for RISC‑V CPU cores, focusing on load/store units, prefetch, and MMU/TLB functionality. Work within a CPU core generator environment (Chisel/FIRRTL) and collaborate with verification, physical implementation, and performance teams to deliver high‑quality silicon IP.
Experience Level
Senior role (title: Staff). The posting requests 3+ years of relevant design experience.
Responsibilities
Primary responsibilities include:
- Architect, design, and implement new CPU features, performance improvements, and ISA extensions using Chisel and RTL.
- Integrate design content into the Chisel/FIRRTL generator and improve the framework for automated configuration, documentation, testbenches, and software packaging.
- Perform initial sandbox verification and collaborate with the design verification team to develop and execute verification plans and tests.
- Work with physical implementation teams to meet frequency, area, and power targets.
- Collaborate with performance modeling teams for exploration and optimization.
- Document microarchitecture and design decisions; participate in collaborative design reviews.
Requirements
Must-have:
- 3+ years of CPU design experience.
- Academic or professional experience with CPU RTL design and implementation.
- Proficiency in Verilog, SystemVerilog, or VHDL for RTL design.
- Strong software engineering skills, including functional and object-oriented programming and test-driven development.
- Good verification principles, familiarity with SVA and coverage, and ability to contribute to verification plans.
- Attention to detail and ability to work effectively on engineering teams.
Nice-to-have:
- Experience with Scala/Chisel, Bluespec, or other hardware-generation DSLs.
- Knowledge of the RISC‑V ISA.
- Experience with out-of-order microarchitecture and verification of load-store units, coherent caches, cache prefetching, or MMU/TLBs.
- Familiarity with Git/GitHub, Jira, and Confluence.
Education Requirements
BS or MS in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field, or equivalent practical experience.
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
