Staff R&D Engineer C

Job Title

Staff R&D Engineer C

Role Summary

Senior R&D engineer responsible for designing, implementing, and maintaining core enhancements to Synopsys' Formality ECO technology. The role focuses on performance‑critical C++ development, debugging large codebases, and delivering reliable ECO solutions used in chip design workflows.

You'll work within the Formality ECO R&D team, collaborating with R&D peers and customer‑facing teams to translate real customer issues into robust, production‑grade solutions.

Experience Level

Senior-level — the posting specifies experience expectations tied to degree (see Education Requirements). Typical experience: 5+ years with a Bachelor's or 3+ years with a Master's.

Responsibilities

Primary responsibilities center on hands‑on delivery, maintenance, and quality improvements of ECO tools and patches.

• Design, implement, and deliver core enhancements to the Formality ECO technology.
• Maintain, debug, and improve existing functionality to enhance performance and memory utilization.
• Lead technical investigations and root-cause analysis for complex, production issues and implement robust fixes.
• Collaborate with R&D teams and customer support to convert ECO problems into practical solutions.
• Promote best practices in code quality, testing, and software design to improve long‑term product health.
• Drive measurable quality and performance improvements that impact customer workflows.

Requirements

Key technical skills and experience required or strongly preferred. Degree requirements are listed separately under Education Requirements.

• Must-have: Strong software development in C++ on UNIX/Linux and solid knowledge of data structures, algorithms, and system design.
• Must-have: Experience working with large, complex commercial codebases and delivering production-grade fixes.
• Must-have: Familiarity with EDA flows and the constraints of semiconductor toolchains.
• Experience with scripting languages (Python, Tcl, Perl, shell) for automation and tooling.
• Familiarity with HDL languages such as Verilog or SystemVerilog, or willingness to learn their nuances.
• Effective communication and presentation skills for technical collaboration and customer interaction.
• Nice-to-have: Knowledge of Logic Equivalence Checking (LEC) and familiarity with modern developer productivity tools (e.g., GitHub Copilot).

Education Requirements

Bachelor's degree in Electrical, Electronics, or Computer Science Engineering with 5+ years of relevant experience, or a Master's degree in those fields with 3+ years of relevant experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.