Staff/Principal Engineer - HBM Design for Test (DFT)

Job Title

Staff/Principal Engineer - HBM Design for Test (DFT)

Role Summary

Senior technical contributor responsible for defining, deploying, and sustaining design-for-test (DFT) solutions across HBM core and base die families, with primary focus on logic-die MBIST architecture, implementation, and manufacturability.

Works across architecture, logic, verification, and physical implementation teams to ensure scalable, testable, and production-ready DFT solutions for HBM products.

Experience Level

Senior — requires substantial experience in DFT or ASIC/SoC logic test. The posting specifies 5+ years of relevant experience.

Responsibilities

Primary responsibilities include ownership of DFT specification, architecture, and program support for HBM logic die MBIST and related test flows.

• Define and document logic-die MBIST architectures, controller interactions, access mechanisms, sequencing, and broadcast behavior.
• Own test definitions and DFT entry flows supporting MBIST, logic test, interface test, and debug modes.
• Collaborate with logic and SoC architects to integrate scalable, generation-extensible DFT features.
• Support RTL debug and functional verification for DFT/MBIST features using Verilog and simulation tools.
• Define checks, assertions, and coverage targets for logic-die test functionality and work with APR teams on physical implementation.
• Address timing closure, clock/reset and scan/MBIST routing impacts, and congestion/power/area tradeoffs related to DFT.
• Provide guidance on DFT-friendly floorplanning and implementation and support late-stage signoff/debug.

Requirements

Must-have technical skills and experience.

• 5+ years of experience in design-for-test, logic test, or SoC/ASIC design roles.
• Strong understanding of MBIST fundamentals and logic test concepts.
• Working knowledge of memory architectures; HBM or DRAM experience preferred.
• Experience defining or influencing DFT requirements, specifications, and verification expectations.
• Experience with RTL debug and verification tools; familiarity with Verilog and simulation flows.
• Practical experience supporting physical implementation issues (timing closure, routing impacts, power/area tradeoffs) for DFT logic.

Nice-to-have:

• Exposure to IEEE 1500, DFT access mechanisms, or broadcast test concepts.
• Experience supporting first silicon bring-up, qualification, or high-volume manufacturing debug.
• Strong cross-functional collaboration and clear written/verbal communication.

Education Requirements

Bachelor's degree in Electrical Engineering or a related field required; Master's degree preferred. (No certifications specified.)

Other

Micron is an equal opportunity employer. Benefits and workplace policies are provided by the employer. Information about benefits is available on Micron's public careers pages.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.