Staff Physical Verification CAD Engineer

Job Title

Staff Physical Verification CAD Engineer

Role Summary

Senior-level role on the Physical Verification CAD team responsible for developing and maintaining physical verification flows, CAD/EDA tools, and automation to support SoC tapeouts.

The engineer will work with layout and design teams, foundry interfaces, and tool vendors to ensure DRC/LVS correctness, performance, and integration into the design flow.

Experience Level

Level: Senior. Guidance: approximately 5–10 years of relevant industry experience.

Responsibilities

Own and improve physical verification CAD flows, tool integrations, and automation to support tapeout and production designs.

• Develop and maintain run sets and rule decks for DRC/LVS using Calibre, ICV and related tools.
• Automate physical verification flows, tool integrations, and layout migration tasks.
• Debug DRC/LVS failures and support designers with validation and issue resolution.
• Support tape-out activities and coordinate design-related foundry interactions.
• Develop validation procedures, test cases, documentation, and user guides for PV flows.
• Evaluate and integrate third-party EDA tools and IP into the design flow.
• Mentor junior engineers and lead technical initiatives in CAD/EDA tool development.

Requirements

Key technical must-haves and preferred skills.

• Minimum 5 years of hands-on experience in CAD/EDA tool development and support within the semiconductor industry.
• Required: Synopsys ICV experience and practical DRC/LVS debugging skills.
• Proficient with industry tools (Cadence, Synopsys, Mentor) and full-custom layout review.
• Scripting proficiency: Tcl, Perl, and/or Python for automation and tool integration.
• Experience automating flows, developing rule decks/run-sets, and improving tool performance.
• Strong cross-functional collaboration and communication skills; experience working with foundry engineers, layout designers, and design teams.
• Proven problem-solving ability and experience leading technical projects.
• Preferred: Mentor Calibre svrf/tvf experience and prior SoC integration/tapeout support.

Education Requirements

Bachelor's or Master’s degree in Computer Science, Electrical Engineering, or a related technical field. The posting specifies 5 to 10 years of related professional experience in addition to the degree requirement.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.