Staff Physical Design Engineer, HBM

Job Title

Staff Physical Design Engineer, HBM

Role Summary

Drive backend implementation of high-performance, low-power digital logic for Micron's High‑Bandwidth Memory (HBM) products. The role covers physical implementation from synthesized netlist through GDSII with emphasis on timing closure, power integrity, manufacturability, and PPA optimization.

Work on complex, multi-hierarchy designs in collaboration with RTL, DFT, CAD, verification, and EDA vendors to deliver signoff-quality physical layouts and improve methodology and automation.

Experience Level

Senior-level role. The posting specifies 7+ years of relevant experience.

Responsibilities

Primary responsibilities include implementation, closure, verification, and automation of physical design for advanced memory products.

• Execute physical design from synthesized netlist to GDSII: floorplanning, placement, clock tree synthesis, routing, and signoff.
• Use AI-enabled tools in the netlist-to-GDS flow to improve productivity and quality.
• Drive timing closure across multiple modes, corners, and scenarios using industry-standard STA tools.
• Analyze and resolve congestion, timing, IR drop, EM, and power integrity issues.
• Develop and refine floorplans, power grids, and clocking strategies for high-performance designs.
• Integrate and place custom analog hard IP macros in a digital-on-top flow.
• Collaborate with RTL designers to influence partitioning, constraints, and micro-architecture early in the cycle.
• Implement and validate low-power techniques including multiple/isolated power domains, power gating, and UPF/CPF-based power intent.
• Execute physical verification (DRC/LVS/ANT/DFM) and support signoff flows.
• Drive functional and timing ECOs to meet design targets.
• Develop scripting and automation (TCL, Python, Perl, Shell) to improve flow robustness and throughput.
• Interface with EDA vendors and internal CAD teams to debug tools and evaluate new tool capabilities.

Requirements

Must-have technical skills and experience are listed below; preferred items are noted separately.

• Strong understanding of the RTL-to-GDSII physical design flow, including floorplanning, P&R, clock distribution, and timing analysis/closure with standard EDA tools and advanced process technologies.
• Experience with full-chip integration, partitioning, and budgeting.
• Solid understanding of power, performance, and area (PPA) tradeoffs.
• Knowledge of low-power architectures such as DVFS, power gating, and multi-voltage designs.
• Proficiency in scripting/programming: TCL, Python, Perl, Shell.
• Experience validating power distribution networks (PDN), IR drop, and electromigration (EM).
• Strong problem-solving skills and ability to debug complex physical design issues.
• Effective verbal and written communication skills and ability to work in cross-functional teams.

Nice-to-have:

• Experience with advanced technology nodes, high-frequency/high-density designs, and complex clocking.
• Familiarity with memory, HBM, or datapath‑intensive designs.
• Understanding of device physics, 3D‑IC technology, advanced packaging, and thermal considerations.

Education Requirements

Required: Bachelor’s degree in Electrical Engineering and 7+ years of related experience. Desired: Master’s degree in Electrical Engineering or Computer Engineering (with ~5+ years experience) as noted in the posting.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.