Staff Physical Design Engineer, HBM

Job Title

Staff Physical Design Engineer, HBM

Role Summary

Lead end-to-end physical design for HBM base die and memory dies, owning floorplanning, placement, timing, power integrity, routing, and signoff for very high macro‑density memory designs. Collaborate with memory, PHY, packaging, clocking, and test teams to enable tape‑out and successful silicon bring‑up.

Experience Level

Senior — 7+ years of hands-on experience in advanced-node physical design.

Responsibilities

Main responsibilities include technical leadership of HBM physical design and signoff.

• Drive end-to-end physical design from netlist through GDSII for HBM base and memory dies.
• Own floorplanning, power planning, placement, CTS, routing, and signoff for high macro-density designs.
• Define HBM-specific physical architecture: channel partitioning, PHY placement, TSV and micro‑bump keep-out regions.
• Lead timing closure across corners for high-speed internal logic and HBM PHY interfaces.
• Drive PDN design and close IR drop, EM, and thermal issues across operating modes.
• Ensure compliance with foundry reliability rules (EM lifetime, via density, TSV stress).
• Collaborate with clocking, PHY, packaging, and test teams on integration, interposer interfaces, and physical alignment of bumps/TSVs/RDLs.
• Own physical signoff readiness: STA, IR/EM, SI, DRC, LVS, density, and reliability.
• Lead ECO strategies, late-stage timing and power fixes, and act as a technical lead in tape-out reviews.
• Mentor engineers and drive PD flow improvements, automation, and reuse; apply AI-assisted automation for LVS/DRC fixes.

Requirements

Required skills, tools, and proven delivery experience for advanced HBM physical design.

• Must-have: Proven tape-out experience on HBM, DRAM, or very large memory-centric designs and ability to lead complex designs through silicon bring-up.
• Tool expertise: Cadence Innovus and/or Synopsys ICC2/Fusion Compiler; PrimeTime STA; RedHawk or equivalent power‑integrity tools; Calibre DRC/LVS and advanced foundry signoff flows.
• Technical fundamentals: Floorplanning and hierarchical PD, timing closure/STA, power integrity (IR/EM), thermal awareness, and physical signoff on advanced technologies.
• Process experience: Experience with FinFET and sub-10nm nodes preferred.
• Leadership: Strong problem-solving, independent execution, cross-team collaboration, and mentoring experience.
• Nice-to-have: Direct experience with HBM2E/HBM3/HBM3E, TSV/micro‑bump layouts, die-to-die interfaces and wide parallel buses, advanced packaging (2.5D/interposer, chiplets), and Tcl/Python scripting for PD flow automation.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.