Senior ASIC Emulation Engineer

Job Title

Senior ASIC Emulation Engineer

Role Summary

Lead the bring-up, deployment, and optimization of pre-silicon emulation platforms to enable hardware/software co-development and accelerate verification cycles for full-chip and system-level ASIC designs. Work closely with architecture, RTL, DFT, DV, firmware, physical design, and validation teams.

Experience Level

Senior level. The role expects experienced engineers; the posting indicates 5+ years of relevant ASIC/SoC emulation experience.

Responsibilities

Primary responsibilities include developing and operating emulation platforms, enabling system-level testing, and improving verification throughput.

• Build, integrate, and maintain full-chip, multi-chip, and system-level emulation models on Palladium, ZeBu, Veloce, or similar platforms.
• Define and evolve emulation strategy, methodology, and workflows across the ASIC organization.
• Compile, map, and optimize RTL for emulation performance, capacity, and stability.
• Develop and integrate transactors, BFMs, speed adapters, and virtualization interfaces for system use cases.
• Support full HW/SW integration in emulation to validate end-to-end workloads and enable firmware and software bring-up.
• Collaborate with DV teams to run targeted emulation tests, adapt DV content, and reduce simulation bottlenecks.
• Run emulation workloads, triage failures, perform root-cause analysis, and coordinate cross-functional debug.
• Maintain and enhance automation for compile flows, regression management, and continuous integration.
• Participate in architecture and microarchitecture reviews and support silicon bring-up and post-silicon validation via test reuse and correlation.
• Manage interactions with external IP or emulation partners as required.

Requirements

Must-have technical skills and experience required to perform the role effectively.

• 5+ years of ASIC/SoC experience focused on emulation and pre-silicon verification.
• Strong SystemVerilog, digital logic, RTL flows, and DV methodology knowledge.
• Hands-on expertise with major emulation platforms (Palladium, ZeBu, Veloce): model build, debug, and performance optimization.
• Proficiency with scripting for automation (Python, Perl, TCL).
• Experience with hardware/software interfaces, embedded processors, firmware bring-up, and C/C++ system-level testing.
• Familiarity with standard buses and protocols (APB/AHB/AXI, JTAG, SPI).
• Experience driving cross-functional debug across RTL, DV, firmware, physical design, and validation teams.
• Understanding of pre- and post-silicon debug methodologies and correlation workflows.

Nice-to-have:

• Experience with FPGA prototyping platforms (HAPS, Protium, custom FPGA boards).
• Experience with low-power modes and power-aware emulation.
• Experience with analog/mixed-signal behavioral models in emulation environments.
• Experience with SERDES and high-speed protocols (PCIe, Ethernet, USB, multi-gigabit PHYs).

Education Requirements

B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field (as stated in the posting).

About the Company

Company: K2 Space

Headquarters: United States

K2 Space specializes in providing high-quality engineering solutions for ASIC, FPGA, and RTL designs. The company focuses on advanced digital design verification and development, catering to the growing demands of the semiconductor industry.