Staff Physical Design Engineer

Job Title

Staff Physical Design Engineer

Role Summary

Senior individual contributor role responsible for owning the full ASIC physical design flow from netlist to GDSII on advanced SoC projects. This is a 1099 contract, fully remote for candidates located in the USA or Canada. Six openings are listed.

The engineer will drive floorplanning, placement, CTS, routing, timing closure, physical verification, and tape-out activities while collaborating with RTL, synthesis, STA, DFT and verification teams.

Experience Level

Senior — 10+ years of hands-on ASIC Physical Design experience (Sr. / Staff level).

Responsibilities

Key responsibilities include:

• Own the complete physical design flow from netlist to GDSII: floorplanning, power planning, placement, CTS, routing, and physical optimization.
• Drive timing closure across PVT corners and implement ECOs to meet tape-out schedules.
• Perform signal integrity, crosstalk, STA, IR drop and EM analysis and implement mitigations.
• Resolve DRC and LVS issues and support physical verification and sign-off flows.
• Optimize designs for power, performance, and area (PPA).
• Collaborate with RTL, DFT, synthesis, STA and verification teams and communicate status across global engineering groups.

Requirements

Must-have skills and constraints:

• 10+ years of hands-on ASIC physical design experience across production tape-outs.
• Proven expertise in floorplanning, power planning, placement & optimization, clock tree synthesis, routing, and timing closure.
• Strong practical knowledge of STA, signal integrity, IR drop and EM analysis, and physical verification flows.
• Experience working with ECO flows and supporting tape-out activities.
• Work authorization: must be legally authorized to work in the USA or Canada without current or future employer sponsorship.

Nice-to-have / preferred:

• Experience on advanced nodes (16nm / 7nm / 5nm / 3nm).
• Experience with CPU, GPU, AI/ML, networking, data center, automotive, HPC, or high-speed SerDes/PCIe/DDR designs.
• Familiarity with EDA tools such as Cadence Innovus, Synopsys ICC2 / Fusion Compiler, PrimeTime, Cadence Tempus, Mentor Calibre, and RedHawk / Voltus.
• Strong communication skills and experience collaborating with distributed/global teams.

Education Requirements

Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EE), Computer Engineering, VLSI, Microelectronics, or a related discipline.

About the Company

Company: Skalen Semi

Skalen Semi is a semiconductor recruitment and staffing firm connecting companies with ASIC/SoC engineering talent. They specialize in contract and full-time placements across physical design, verification, RTL, and other chip-design disciplines for advanced process nodes.