Staff Packaging Engineer

Job Title

Staff Packaging Engineer

Role Summary

Lead package and SiP physical design efforts for high-performance server SoCs within Qualcomm's Data Center team. The role focuses on package selection, layout, verification, and cross-functional optimization to meet mechanical, electrical, and thermal requirements for next-generation products.

Experience Level

Senior. Minimum qualifications specify Bachelor's +4 years, Master's +3 years, or PhD +2 years of relevant experience; preferred candidates typically have ~5+ years in packaging or related engineering roles.

Responsibilities

Primary responsibilities include package selection, physical design, verification, and cross-functional coordination.

• Own advanced package selection and optimize package structures and configurations for new product generations.
• Design and layout package/SiP physical implementations and drive tape-out readiness.
• Coordinate with electrical, mechanical, thermal, and product teams to meet SI/PI and thermal requirements.
• Define and implement design verification and automation strategies for package release flows.
• Optimize package pinout and collaborate with BU PD on floorplan and bump placement to minimize package size.
• Drive methodology, tooling, and efficiency improvements with vendors and internal developers.
• Evaluate and integrate new CAD tools and verification flows.
• Ensure package designs meet DFM, DRC, and electrical rule requirements.

Requirements

Technical must-haves and preferred skills for successful candidates.

• Experience with Cadence Advanced Package Designer (APD) & SiP or Siemens Xpedition Package Designer (xPD).
• Familiarity with Constraint Manager for setting up DFM and electrical rules.
• Use of in-line DRC, DFM verification, and electrical rule checking (ERC).
• Basic signal-integrity knowledge for high-speed I/O, transmission lines, and electromagnetic field concepts.
• Knowledge of IC packaging structures and chip-package-board interactions.
• Experience in package physical design, layout, and tape-out processes.

• Familiarity with Cadence Allegro platform tools and SI/PI tools (XtractIM, PowerSI, HFSS, Q3D, etc.).
• Experience with package model extraction, S-parameters, RLGC models, and Calibre tools.
• Understanding of substrate manufacturing, assembly/substrate technologies (Flip chip BGA, 2.5D/3D interposer), and manufacturing failure modes.
• Knowledge of high-speed layout constraints (crosstalk mitigation, differential pairs).

Education Requirements

Bachelor's degree in Chemical, Electrical, Mechanical Engineering or a related field with 4+ years of System/Package Design/Technology Engineering experience; OR Master's degree in those fields with 3+ years (preferred listings also cite Master's with 5+ years); OR PhD in those fields with 2+ years. Related technical degrees or equivalent professional experience are acceptable per the posted minimums.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.