Staff Layout Engineer – DPG Layout

Job Title

Staff Layout Engineer – DPG Layout

Role Summary

Lead physical implementation and layout automation for critical analog, mixed-signal, and custom digital blocks at block and full-chip levels. Collaborate with design, CAD, verification, reliability, and program teams to deliver manufacturable layouts on advanced CMOS nodes.

Develop AI-enabled and automated workflows, drive verification automation, and mentor engineers on layout fundamentals and design-for-yield practices.

Experience Level

Senior-level — typically requires 6+ years of analog/custom layout design experience in advanced CMOS nodes.

Responsibilities

Primary responsibilities include:

• Own block- and full-chip layout implementation for analog, mixed-signal, and custom digital IP.
• Lead AI-assisted and automated placement, routing, and optimization workflows.
• Develop and deploy automation for floorplanning, parasitic estimation, layout consistency checks, and repetitive task elimination using SKILL, Python, TCL, or agent-based flows.
• Perform and automate physical verification activities (DRC, LVS, Antenna, Yield, ESD, TOTEM, EM/IR) and debug verification failures to closure.
• Plan area and cycle-time estimates, predict risks, and ensure on-time delivery of layout partitions.
• Mentor engineers on analog layout fundamentals, automation-first approaches, and design-for-quality/yield practices.
• Collaborate with cross-functional teams to communicate technical risks, schedule impacts, and optimization opportunities.
• Identify manual bottlenecks and convert them into scalable automated flows.

Requirements

Must-have technical skills and experience:

• 6+ years of analog/custom layout design experience in advanced CMOS nodes.
• Strong practical experience with Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS and ownership of verification closure.
• Experience laying out critical analog blocks such as temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, charge pumps.
• Hands-on experience with memory layouts (DRAM, SRAM, CAM, OTP) and array-to-periphery integration.
• Deep understanding of layout fundamentals: matching, symmetry, EM, latch-up, coupling, crosstalk, IR-drop, shielding, guard rings, parasitics.
• Ability to interpret design intent and constraints to produce manufacturable layouts.
• Proven track record developing and scaling AI-driven automation and AI-assisted layout methodologies.
• Strong problem-solving skills in physical verification, debug, and layout optimization focused on yield improvement.

Education Requirements

B.Tech in Electronics, Electronics & Communication, or VLSI Engineering; M.Tech in VLSI Design, Microelectronics, or Electronics Engineering.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.