Staff Layout Engineer — DPG Layout

Job Title

Staff Layout Engineer — DPG Layout

Role Summary

Lead physical implementation and verification of critical analog, mixed-signal, and custom digital blocks at advanced CMOS nodes. Own block- and partition-level layouts, drive AI-enabled automation for layout and verification, and mentor engineers to deliver manufacturable, high-yield designs on schedule.

Experience Level

Senior — typically 6+ years of relevant analog/custom layout experience as stated in the posting.

Responsibilities

Primary responsibilities include hands-on layout ownership, automation, verification, delivery management, and technical leadership.

• Own development and physical implementation of analog, mixed-signal, and custom digital blocks; block-level and full-chip layout ownership.
• Lead layout implementation using AI-assisted and automated workflows, including copilot/agentic AI flows and rule-aware automation.
• Perform and automate layout verification (DRC, LVS, Antenna, Yield, ESD, TOTEM, EM/IR) and quality checks.
• Drive on-time delivery of blocks and partition layouts with risk prediction and mitigation plans.
• Develop and deploy AI-enabled methodologies for semi-automated floorplanning, parasitic estimation, consistency checks, and repetitive task elimination.
• Provide technical leadership for planning, area and cycle-time estimation, delegation, and execution.
• Guide and mentor engineers on analog layout fundamentals, automation-first approaches, and design-for-quality/for-yield practices.
• Collaborate with Design, CAD, Verification, Reliability, and Program Management to communicate technical risks and optimization opportunities.
• Identify manual bottlenecks and convert them into scalable automated flows.

Requirements

Must-have technical skills and experience.

• 6+ years of analog/custom layout design experience in advanced CMOS technology nodes.
• Strong expertise with Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS, with hands-on ownership of verification closure.
• Proven layout experience for critical analog blocks (examples: temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, charge pumps).
• Hands-on experience with memory layouts (DRAM, SRAM, CAM, OTP) and array-to-periphery integration.
• Deep understanding of analog layout fundamentals: matching and symmetry, EM, latch-up, coupling/crosstalk, IR-drop, shielding, guard-ring strategies, and parasitic effects.
• Ability to interpret design intent and constraints and translate them into manufacturable layouts.
• Proven experience defining, developing, and scaling AI-driven automation and AI-assisted methodologies for complex layout workflows.
• Strong problem-solving skills in physical verification, debug, and layout optimization focused on improving yield.
• Experience automating repetitive layout tasks using SKILL, Python, TCL, or agent-based flows.

Education Requirements

B.Tech in Electronics, Electronics & Communication, or VLSI Engineering; M.Tech in VLSI Design, Microelectronics, or Electronics Engineering as specified in the posting.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.