Staff Layout Engineer - DPG Layout

Job Title

Staff Layout Engineer - DPG Layout

Role Summary

Responsible for ownership and physical implementation of critical analog, mixed-signal, and custom digital blocks at block and full-chip levels for advanced CMOS nodes. The role leads layout implementation, verification closure, and development of AI-assisted and automated layout workflows.

Works across Design, CAD, Verification, Reliability, and Program Management to deliver predictable, manufacturable layouts and to mentor engineers on layout fundamentals and automation-first practices.

Experience Level

Senior level. The posting requests 6+ years of relevant analog/custom layout experience; title indicates senior/Staff-level responsibility.

Responsibilities

Primary accountabilities include technical leadership of layout delivery, automation, verification, and mentoring.

• Own development and physical implementation of analog, mixed-signal, and custom digital blocks, including block-level and full-chip layouts.
• Lead layout implementation using AI-assisted and automated workflows, including copilot-based assistants and agentic AI flows.
• Perform and automate layout verification (DRC, LVS, Antenna, Yield, ESD, TOTEM, EM/IR) and quality checks with hands-on verification closure.
• Drive on-time delivery of blocks and partition-level layouts with risk prediction and mitigation plans.
• Develop and deploy AI-enabled methodologies for floorplanning, parasitic estimation, consistency checks, and elimination of repetitive tasks via SKILL, Python, TCL or agent-based flows.
• Provide technical leadership in planning, area and cycle-time estimation, delegation and execution.
• Guide and mentor engineers in analog layout fundamentals, automation-first approaches, design-for-quality and design-for-yield practices.
• Identify manual bottlenecks and convert them into scalable automated flows.

Requirements

Must-have technical skills and experience.

• 6+ years of experience in analog/custom layout design in advanced CMOS technology nodes.
• Strong expertise with Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS, including ownership of verification closure.
• Proven experience in layout of critical analog blocks (examples: temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, charge pumps).
• Hands-on experience with memory layouts (DRAM, SRAM, CAM, OTP) and array-to-periphery integration.
• Deep understanding of analog layout fundamentals: matching/symmetry, EM, latch-up, coupling, crosstalk, IR-drop, shielding, guard-ring strategies, parasitic effects.
• Ability to interpret design intent and constraints and translate them into manufacturable, high-quality layouts.
• Proven expertise defining, developing, and scaling AI-driven automation and AI-assisted methodologies for complex layout workflows.
• Demonstrated problem-solving skills in physical verification, debug, and layout optimization focused on yield improvement.

Education Requirements

B.Tech in Electronics, Electronics & Communication, or VLSI Engineering; M.Tech in VLSI Design, Microelectronics, or Electronics Engineering.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.