Staff Layout Engineer - DPG Layout

Job Title

Staff Layout Engineer - DPG Layout

Role Summary

Responsible for ownership and physical implementation of critical analog, mixed-signal and custom-digital blocks at block and full-chip level. Lead the application of AI-assisted and automated layout workflows to accelerate placement, routing, verification and manufacturability.

Experience Level

Senior — requires 6+ years of experience in analog/custom layout design in advanced CMOS technology nodes.

Responsibilities

Primary responsibilities include hands-on layout ownership, verification closure, automation, and technical leadership.

• Own block- and partition-level layout implementation for analog, mixed-signal and custom digital blocks; deliver on schedule with predictable quality and mitigation plans.
• Lead layout implementation using AI-assisted and rule-aware automated workflows (copilot/agentic AI flows) to speed placement, routing and optimization.
• Perform and automate physical verification tasks including DRC, LVS, Antenna, Yield, ESD, TOTEM, EM/IR and quality checks; drive verification closure.
• Develop and deploy semi-automated floorplanning, parasitic estimation, layout consistency checks and best-practice enforcement.
• Identify manual bottlenecks and convert them into scalable automated flows; estimate area and cycle time and plan execution.
• Collaborate with Design, CAD, Verification, Reliability and Program teams; communicate technical risks, schedule impacts and optimization opportunities.
• Guide and mentor engineers on analog layout fundamentals, automation-first approaches and design-for-yield practices.

Requirements

Must-have technical skills and experience; nice-to-have items called out when available.

• 6+ years of analog/custom layout experience in advanced CMOS nodes.
• Hands-on expertise with Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS and ownership of verification closure.
• Experience laying out critical analog blocks such as temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators and charge pumps.
• Experience with memory layouts (DRAM, SRAM, CAM, OTP) and array-to-periphery integration.
• Deep understanding of analog layout fundamentals: matching, symmetry, EM, latch-up, coupling, crosstalk, IR-drop, shielding and guard-ring strategies.
• Proven ability to interpret design intent and constraints into manufacturable layouts and to debug/optimize for yield.
• Experience defining, developing and scaling AI-driven automation and AI-assisted methodologies for complex layout workflows.
• Proficiency scripting or automating repetitive layout tasks using SKILL, Python, TCL or agent-based flows (preferred).

Education Requirements

B.Tech in Electronics, Electronics & Communication, or VLSI Engineering; M.Tech in VLSI Design, Microelectronics, or Electronics Engineering.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.