Staff Layout Designer - Pathfinding

Job Title

Staff Layout Designer - Pathfinding

Role Summary

Develop and prepare multi-dimensional layouts and detailed drawings of semiconductor devices from schematics and provided geometry. Lead major block developments, verify data integrity, and improve layout efficiency through automation and new methodologies. Collaborate with design, verification, CAD and other cross-functional teams across global sites.

Experience Level

Senior — typically requires around 10+ years of direct semiconductor layout design experience.

Responsibilities

Primary responsibilities include delivering high-quality IC layouts, leading workstreams, and mentoring team members.

• Develop and prepare multi-dimensional layouts and detailed drawings from schematics and geometry.
• Lead, plan, and deliver major blocks and product revisions; drive schedule and resource allocation to meet deadlines.
• Improve layout efficiency by developing automation, tools, and new methodologies.
• Perform floor‑planning, signal‑planning and power‑planning for blocks and chips.
• Perform physical verification analysis and debug layout issues.
• Communicate and coordinate with global teams (TD, design, verification, CAD) to ensure design integrity.
• Mentor and train junior layout designers; contribute to group management and technical innovation.

Requirements

Must-have technical skills and experience followed by commonly preferred qualifications.

• Must-have: ~10+ years direct semiconductor layout design experience focused on IC layout and block delivery.
• Must-have: Deep working knowledge of EDA tools such as Cadence Virtuoso, Synopsys, and Calibre.
• Must-have: Strong debugging and root-cause analysis skills; proven ability to resolve complex layout and verification issues.
• Must-have: Skilled in custom layout techniques, floor‑planning, signal‑planning, and power‑planning; thorough understanding of design rules.
• Must-have: Strong verbal and written communication skills and experience collaborating across functions and sites.
• Preferred: Project leadership experience in quality optimization and die-size shrinkage.
• Preferred: IC layout experience with NAND, DRAM and/or SRAM technologies.
• Preferred: Programming skills and experience leveraging AI or automation in the layout workflow.

Education Requirements

AS or Bachelor's degree in Electronics, Electrical Engineering, or a related field is specified in the minimum qualifications; a BS degree is listed as preferred. The role pairs the degree requirement with extensive practical experience (about 10+ years) in semiconductor layout design.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.