Staff Layout Designer

Job Title

Staff Layout Designer

Role Summary

Senior layout engineer responsible for producing high-quality analog, mixed-signal and periphery layouts for memory products. Works with design, CAD, test and technology teams to floor-plan, place, route, verify, and tape out mid-size to critical blocks.

Focus areas include layout implementation, LVS/DRC/debug, ECO/LCO/DFM execution, and mentoring junior designers to meet schedule and quality targets.

Experience Level

Senior — 7+ years of layout experience (Staff-level expectations).

Responsibilities

Primary responsibilities include design implementation, verification, coordination, and delivery of layouts for memory-related products.

• Implement and deliver high-quality layouts for periphery and core/pitch blocks.
• Use Cadence VXL for layout tasks on periphery blocks.
• Debug and resolve LVS, DRC and layout verification issues.
• Create layouts for critical analog/mixed-signal blocks (temperature sensors, PLL, ADC, DAC, LDO, bandgap, reference generators, charge pumps, current mirrors, comparators, differential amplifiers, etc.).
• Apply analog layout fundamentals: matching, electromigration, latch-up, coupling, crosstalk, IR-drop, and parasitic management.
• Plan and execute floor-planning, placement and routing to meet area, power and performance trade-offs.
• Execute ECO/LCO and DFM tasks; support multiple tape-outs.
• Coordinate schedules and deliverables with TD, design, CAD and layout teams; negotiate technical trade-offs.
• Mentor junior layout designers and organize resource allocation to meet deadlines.

Requirements

Must-have technical skills and experience to perform the role.

• 7+ years of hands-on IC layout experience, preferably in memory or mixed-signal environments.
• Proficiency with Cadence VXL for periphery and block-level layout.
• Proven LVS/DRC/debug skills and experience resolving layout verification issues.
• Hands-on layout experience for critical analog blocks (PLL, ADC/DAC, LDO, bandgap, reference generators, charge pumps, current mirrors, comparators, differential amplifiers, temperature sensors).
• Strong understanding of analog layout principles: matching, electromigration, coupling/crosstalk, IR-drop, parasitics, and their impact on speed, capacitance, power and area.
• Experience with floor-planning, placement, routing, and design-rule compliance to deliver production-quality layouts.
• Experience with ECO/LCO and DFM practices and tape-out processes.
• Effective problem-solving, cross-team coordination, and mentoring skills.

Nice-to-have:

• Multiple tape-out support experience.
• Familiarity with automation and AI-assisted layout tools.
• Experience specifically with NAND or other memory product flows.

Education Requirements

Not specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.