Staff Layout Design Engineer — Da Nang

Job Title

Staff Layout Design Engineer — Da Nang

Role Summary

Lead physical layout design for advanced memory IP (SRAM, ROM, eDRAM) at cell, array, and peripheral levels. Work on ensuring manufacturability, performance, and first-pass silicon success while coordinating with circuit designers, process engineers, and verification teams.

Experience Level

Senior-level; at least 5 years of hands-on custom layout design experience focused on memory structures.

Responsibilities

Primary responsibilities include leading layout work, resolving verification issues, optimizing designs, and mentoring engineers.

• Lead memory IP layout for SRAM, ROM, and eDRAM at transistor, cell, array, and peripheral circuit levels.
• Ensure layouts comply with foundry process design rules and memory-specific constraints; resolve DRC/LVS issues.
• Optimize layouts for area, performance, power, yield, and manufacturability.
• Perform RC extraction and parasitic analysis on dense arrays and iterate designs to meet timing and signal integrity targets.
• Investigate and debug reliability issues such as electromigration, IR drop, and soft error susceptibility.
• Collaborate with circuit designers, verification engineers, process teams, and customers to deliver tapeout-ready layouts.
• Mentor junior layout engineers and promote best practices and tooling efficiency.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

• Must-have: Minimum 5 years of hands-on memory layout experience (SRAM/ROM/eDRAM) with deep transistor- and cell-level expertise.
• Must-have: Proficiency with layout and physical verification tools such as Custom Compiler, Virtuoso, or IC Compiler.
• Must-have: Strong working knowledge of foundry process design rules, DRC/LVS verification flows, and memory-specific layout constraints.
• Must-have: Experience with RC extraction, parasitic analysis, and iterating layouts to meet signal integrity and timing margins.
• Must-have: Proven ability to debug complex layout and reliability issues and to work cross-functionally to resolve them.
• Nice-to-have: Prior experience mentoring engineers and driving layout automation or process improvements.
• Nice-to-have: Broad experience across multiple memory types and advanced process nodes.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Telecommunication, Physics, or a related technical field. (Degree fields listed as preferred in the source.)

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.