Staff Interface IP Verification Engineer (Pre-Silicon)

Job Title

Staff Interface IP Verification Engineer (Pre-Silicon)

Role Summary

Lead pre-silicon verification for complex Interface IP (PCIe, CXL, DDR, Ethernet), delivering scalable, reusable UVM-based testbenches from architecture review through signoff and customer release.

Work across architecture, design, and verification teams to close functional coverage, debug protocol and system-level issues, and mentor verification engineers.

Experience Level

Senior (Staff level). The posting specifies at least 5 years of hands-on ASIC/SoC verification experience.

Responsibilities

Key responsibilities include ownership of verification strategy, environment architecture, and delivering silicon-ready verification results.

• Own end-to-end verification of Interface IP from architecture review to customer release.
• Architect and build scalable UVM-based verification environments and reusable VIP components.
• Define verification strategies, detailed test plans, and map coverage goals to integration risks.
• Develop constrained-random, coverage-driven testbenches using SystemVerilog and UVM.
• Drive functional coverage closure and write targeted tests to close gaps prior to tapeout.
• Debug complex RTL, protocol, and system-level issues using simulators and waveform/assertion analysis.
• Mentor engineers on UVM, coverage techniques, and debugging; contribute to verification infrastructure and process improvements.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

• Must-have: Deep expertise in SystemVerilog and UVM, including constrained-random testbenches and functional coverage models.
• Must-have: Proven experience verifying protocol compliance and system-level interactions for one or more of PCIe, CXL, DDR, or Ethernet.
• Must-have: Experience driving coverage closure and building reusable verification components that scale across product variants.
• Must-have: Strong debugging skills across RTL, verification infrastructure, and protocol layers; experience with simulators such as VCS, ModelSim, Xcelium, or Questa.
• Nice-to-have: Experience with verification IP development, assertion-based verification, formal methods, modern SoC architectures, high-speed SerDes, or cache coherency protocols.

Education Requirements

Requires a Bachelor's or Master's degree in Electrical Engineering or Computer Engineering. The posting also specifies at least 5 years of hands-on ASIC/SoC verification experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.