Staff Implementation Engineer

Job Title

Staff Implementation Engineer

Role Summary

Join Arm's Solutions Engineering group to lead RTL-to-GDSII physical implementation and tapeout of CPU, GPU, interconnect and SoC designs. This is a senior, hands-on physical design role responsible for delivering timing, power, and signoff closure on complex, high-performance builds.

Experience Level

Senior - typically requires 10+ years of hands-on ASIC physical implementation experience.

Responsibilities

Drive end-to-end implementation and signoff for complex IPs and SoCs, working directly with architecture, RTL, DFT and methodology teams.

• Own RTL-to-GDSII physical implementation and tapeout for processor cores, GPUs, interconnects, subsystems and SoC builds.
• Collaborate with RTL and architecture teams to translate PPA requirements into implementation targets.
• Drive timing closure across MCMM scenarios, including setup, hold, clocking and complex path analysis.
• Ensure readiness and closure for STA, physical verification, power integrity and tapeout signoff requirements.
• Coordinate with DFT teams to implement and close scan, test modes and other test requirements.
• Debug implementation and EDA-tool issues and work with EDA vendors and methodology teams to resolve them.
• Lead implementation reviews, identify risks early and define mitigation plans to ensure successful tapeout.
• Develop and improve implementation methodologies, automation and flows to improve quality and execution efficiency.
• Collaborate across geographically distributed teams and drive issues to closure with minimal direction.

Requirements

Must-have technical skills and experience.

• 10+ years of hands-on ASIC physical build / implementation experience with ownership of complex builds from RTL to GDSII and successful tapeout.
• Deep, practical expertise across the full implementation lifecycle: synthesis, floorplanning and partitioning, PDN planning, placement, congestion optimization, clock tree synthesis and clock optimization, routing and post-route optimization.
• Strong MCMM timing-closure experience including timing constraints, clocking methodologies, OCV, crosstalk/SI and advanced-node timing issues.
• In-depth low-power implementation knowledge: UPF, multi-voltage domains, power gating, level shifters, isolation and voltage/frequency scaling.
• Experience owning STA, physical verification, power integrity checks and other tapeout signoff activities.
• Proven ability to debug complex EDA-tool and implementation issues and engage with vendors and internal methodology teams.
• Strong scripting and automation skills (Tcl, Python, Perl, shell and/or Make).
• Experience coordinating with DFT teams to implement and verify scan/test modes and related requirements.

Nice-to-have:

• Experience implementing high-performance Arm CPUs, GPUs, coherent interconnects or large, high-frequency SoCs.
• Familiarity with advanced process nodes, hierarchical physical design and integration of multiple IPs/subsystems.
• Experience with structured clock architectures and complex clock-distribution methodologies.
• Direct experience working with foundries, EDA vendors and physical IP providers on implementation and signoff issues.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering or a related technical field, a Master's degree, or equivalent practical experience. The posting explicitly allows equivalent professional experience in lieu of a degree.

About the Company

Company: Arm

Headquarters: Cambridge, United Kingdom

ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.