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Staff Formal Verification Engineer

SiFive
September 16, 2026
Full-time
On-site
Bengaluru, Karnataka, India
Verification Jobs, Level - Senior

Job Title

Staff Formal Verification Engineer

Role Summary

Lead the formal verification strategy and execution for complex out-of-order (OOO) processor blocks and other digital subsystems. Work with design and verification teams to create formal test plans, implement proofs, maintain assertion libraries, and integrate formal environments (Chisel) into the verification flow.

This role focuses on reducing verification complexity through formal abstraction techniques and delivering sign-off-quality proofs for production hardware.

Experience Level

Senior - typically 7+ years of experience in formal verification of digital hardware design.

Responsibilities

Primary responsibilities include defining formal verification scope, implementing proofs, and mentoring others.

  • Identify blocks suitable for formal verification and define sign-off criteria.
  • Create formal test plans and select properties to implement.
  • Implement and maintain formal verification environments (Chisel-based setups).
  • Apply formal abstraction techniques to make proofs tractable and prove correctness of DUTs.
  • Debug RTL issues exposed by formal checks and work with designers to resolve failures.
  • Develop and maintain assertion libraries and formal proof repositories.
  • Automate verification workflows with scripts and tooling enhancements.
  • Review formal setups and proofs with design and verification teams; provide training and guidance.

Requirements

Must-have skills and technologies required for success in this role.

  • 7+ years experience in formal verification of digital hardware designs (experience with processor blocks is highly valued).
  • Extensive experience with formal abstraction techniques and delivering sign-off-quality proofs.
  • Familiarity with industry-standard formal tools such as VC Formal and JasperGold.
  • Practical knowledge of Hardware Description and Verification Languages: VHDL, Verilog/SystemVerilog.
  • Experience implementing and maintaining formal environments and assertion libraries.
  • Strong debugging, logical reasoning, and attention to detail.
  • Good interpersonal skills and ability to mentor and collaborate across teams.
  • Nice-to-have: experience with out-of-order processors, vector execution engines, and object-oriented programming.

Education Requirements

Bachelor's or Master’s degree in Engineering (electrical/computer engineering or related field) as listed in the posting.


About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.

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Date Posted: 2026-09-16