Staff Engineer, VLSI Design Engineering

Job Title

Staff Engineer, VLSI Design Engineering

Role Summary

Lead digital design and delivery of NAND Flash memory logic, covering microarchitecture, RTL implementation, verification, synthesis, and timing closure. Work within the Memory Technology Group to drive productization, cross-team technical specifications, and post-silicon debug.

Experience Level

Senior — minimum 5 years of relevant industry experience required.

Responsibilities

Deliver and integrate digital logic for NAND Flash memory products and mentor junior engineers.

• Architect and implement RTL (Verilog) for complex logic blocks.
• Perform RTL linting, clock domain crossing (CDC) analysis, and design integration.
• Lead synthesis, DFT insertion, static timing analysis, and timing closure activities.
• Support place-and-route, clock-tree synthesis, extraction, and physical verification activities with relevant teams.
• Participate in post-silicon evaluation, debug, and product bring-up.
• Balance design trade-offs across power, performance, area, scalability, and modularity.
• Interface with internal and external stakeholders to define technical requirements and features.
• Provide technical guidance and mentor junior engineers.

Requirements

Key qualifications and skills; degree details are summarized in Education Requirements below.

• Must-have: Minimum 5 years of relevant experience in digital/logic design and chip-level integration; experience across full product lifecycle.
• Must-have: Practical knowledge of the complete logic design flow from RTL to GDSII (RTL coding/simulation, synthesis, STA, equivalence checking, DFT, place-and-route, physical verification).
• Must-have: Working knowledge of NAND flash memory cell operations and algorithms for program/read/erase.
• Must-have: Strong verbal and written communication and demonstrated ability to work cross-functionally.
• Nice-to-have: Experience designing for low-power operation and familiarity with device physics and process integration.
• Nice-to-have: Familiarity with NAND Flash analog, core, datapath and IO circuit interactions.
• Nice-to-have: Proficiency with digital EDA tools such as Synopsys Design Compiler, Cadence Genus/RTL Compiler, Synopsys PrimeTime/Cadence Tempus, and Synopsys ICC / Cadence Innovus/Encounter.
• Nice-to-have: Experience with revision control and EDA formats (Liberty, SDC); programming in C/C++, Python, or Perl.

Education Requirements

Master of Science in Electrical Engineering (MSEE) required plus 5 years of relevant industry experience.

About the Company

Company: SanDisk

Headquarters: Milpitas, California, United States

SanDisk is a global designer and manufacturer of flash memory and storage solutions, including NAND Flash and SSD products for consumer and enterprise markets. Known for innovation, performance and quality, it operates advanced manufacturing facilities recognized by the World Economic Forum and supports global supply chains with memory technologies.