Staff Engineer – Synthesized Model IP Design

Job Title

Staff Engineer 6 Synthesized Model IP Design

Role Summary

Lead development and delivery of synthesizable IP models for emulation and FPGA prototyping platforms. Provide technical leadership across RTL development, C/C++ reference modeling, FPGA implementation, emulation, and system integration to enable platform bring-up and software development.

The role partners with architecture, verification, software, and platform teams, contributes to micro-architecture and implementation decisions, and mentors junior engineers.

Experience Level

Senior level. Target candidate: 10+ years of experience in ASIC/SoC/FPGA/RTL design, emulation, or prototyping domains.

Responsibilities

Primary responsibilities include delivering synthesizable IP and supporting platform validation and integration.

• Design and develop synthesizable IP models targeting emulation and FPGA prototyping.
• Contribute to architecture and micro-architecture definition and design reviews.
• Implement and optimize RTL (Verilog/SystemVerilog) for functionality, performance, area, and timing closure.
• Develop and maintain C/C++ reference models and validation frameworks aligned with RTL.
• Drive IP integration, debug, validation, and bring-up across simulation, emulation, and FPGA environments.
• Support FPGA implementation: synthesis, timing closure, hardware validation, and performance tuning.
• Coordinate with architecture, verification, software, and system teams to enable platform and software bring-up.
• Prepare project plans, estimate schedules, identify technical risks, and drive execution to milestones.
• Mentor 2 64 engineers, perform code reviews, and promote engineering best practices.
• Promote automation and AI-assisted design methodologies to improve productivity.

Requirements

Must-have technical skills and domain experience; education details are listed separately below.

• Extensive experience developing synthesizable models and RTL (Verilog/SystemVerilog) for ASIC/SoC projects.
• Proven track record delivering complex IP, subsystem, or SoC projects through validation.
• Strong C/C++ skills for reference models and validation frameworks.
• Familiarity with on-chip protocols and system integration: AXI/AHB/APB, CDC, reset and power management.
• Experience with Git, CI/CD workflows, and scripting (Python, Tcl, Perl, Shell).
• Hands-on FPGA prototyping experience (Xilinx/AMD UltraScale+, Versal) including Vivado flows, synthesis, implementation, and timing closure.
• Familiarity with emulation platforms and co-emulation methods (e.g., Veloce, Zebu, Palladium) and technologies such as SCE-MI and DPI-C.
• Strong debugging, system-level analysis, and cross-functional communication skills.

Nice-to-have:

• Multi-FPGA partitioning and large-scale SoC prototyping experience.
• Experience with HLS, cloud-based EDA workflows, and AI-assisted semiconductor design tools.
• Exposure to software bring-up and emulation-based validation at scale.

Education Requirements

Degree expected: Bachelor's, Master's, or PhD in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related technical field. Qualcomm's minimum-qualification structure indicates acceptable combinations of degree and experience (e.g., Bachelor's + 4+ years, Master's + 3+ years, PhD + 2+ years). Equivalent technical work experience in place of a degree is implicitly recognized via those alternative experience thresholds.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.