Staff Engineer – Synthesized Model IP Design

Job Title

Staff Engineer – Synthesized Model IP Design

Role Summary

Staff Engineer responsible for developing synthesizable IP models for emulation and FPGA prototyping platforms. The role leads RTL and reference-model implementation, FPGA bring-up, and cross-functional integration to enable platform validation and software bring-up.

Works with architecture, verification, software, and platform teams; provides technical leadership and mentors a small engineering team.

Experience Level

Senior — typically requires 10+ years of experience in ASIC/SoC/FPGA/RTL design and emulation/prototyping domains.

Responsibilities

Core responsibilities include design, integration, validation, and technical leadership.

• Design and deliver synthesizable IP models for emulation and FPGA prototyping platforms.
• Define architecture and micro-architecture; participate in design reviews and implementation planning.
• Develop and optimize RTL (Verilog/SystemVerilog) for function, performance, area, and timing closure.
• Implement and maintain C/C++ reference models aligned with RTL.
• Integrate IP, debug and validate across simulation, emulation, and FPGA environments; support bring-up.
• Perform FPGA implementation tasks: synthesis, timing closure, hardware validation, and optimization.
• Prepare project plans, estimate schedules, identify risks, and drive execution to milestones.
• Mentor 2–4 engineers; lead code reviews and engineering best practices.
• Promote automation and AI-assisted design methodologies to improve productivity.

Requirements

Key technical must-haves and preferred skills.

Must-have:

• 10+ years of experience in ASIC, SoC, FPGA, RTL design, or emulation/prototyping domains.
• Strong RTL design and synthesizable model development experience (Verilog/SystemVerilog).
• Strong C/C++ skills for reference models and validation frameworks.
• Experience with FPGA flows and tools (Xilinx/AMD UltraScale+, Versal; Vivado) including synthesis and timing closure.
• Experience with emulation platforms (e.g., Veloce, Zebu, Palladium) and co-emulation methodologies (SCE-MI, DPI-C, transactors).
• Familiarity with AXI/AHB/APB protocols, CDC, reset architecture, power management, and system-level integration.
• Experience with Git, CI/CD workflows, and scripting (Python, Tcl, Perl, Shell).

Nice-to-have:

• Experience with large-scale SoC prototyping, multi-FPGA partitioning, and system integration.
• Familiarity with AI-assisted semiconductor design tools, HLS methodologies, or cloud-based EDA workflows.
• Protocol experience (LPDDR5/5X/6, PCIe, Ethernet, USB, MIPI, I2C/I3C, UART).

Education Requirements

Bachelor's, Master's, or PhD in Computer Science, Electrical/Electronics Engineering, or a related engineering field. Minimum qualification combinations listed in the posting: Bachelor's + 4+ years experience, Master's + 3+ years, or PhD + 2+ years. (Degrees or equivalent technical experience expected for senior technical roles.)

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.