Staff Engineer – STA Methodology/CAD

Job Title

Staff Engineer – STA Methodology/CAD

Role Summary

The Staff Engineer will develop, deploy, and enhance static timing analysis (STA) methodologies and CAD infrastructure for complex SoCs. The role partners with RTL, synthesis, physical design, DFT and CAD teams to drive timing signoff and timing closure across multiple projects.

Work includes methodology definition, automation, signoff flows, tool evaluation, debugging complex timing issues, and mentoring junior engineers.

Experience Level

Senior - typically requires 7+ years of experience in STA, timing signoff, timing methodology, or CAD/EDA methodology development.

Responsibilities

Primary responsibilities focus on STA methodology, timing signoff flows, automation, and cross-team collaboration.

• Define, develop, and improve STA methodologies for block, subsystem, and full-chip designs.
• Drive timing signoff flows including MMMC analysis, constraint validation, ECO methodologies, and correlation strategies.
• Develop automation and infrastructure (Tcl/Python/Perl) to improve timing analysis efficiency and turnaround.
• Own methodology for timing closure, reporting, constraint management, and signoff quality metrics.
• Collaborate with RTL, synthesis, physical design, DFT, and CAD teams to enable timing convergence.
• Promote advanced timing techniques such as SOCV/AOCV, hierarchical STA, and signoff optimization flows.
• Debug complex timing issues and deliver scalable solutions across projects.
• Evaluate and deploy new EDA tool capabilities and AI-driven timing closure approaches.
• Mentor junior engineers and provide technical leadership on methodology initiatives.

Requirements

Essential technical skills and experience required for day-to-day success.

Must-have:

• 7+ years experience in STA, timing signoff, timing methodology, or CAD/EDA methodology development.
• Deep knowledge of Static Timing Analysis (STA), MMMC timing signoff, and SDC constraints.
• Experience with setup/hold closure methodologies, ECO and timing convergence techniques, and SOCV/AOCV derates.
• Practical experience with Synopsys PrimeTime or Cadence Tempus.
• Strong scripting skills in Tcl and Python to build automation and infrastructure.

Nice-to-have:

• Experience with advanced process nodes (7nm and below).
• Background in developing timing automation frameworks, dashboards, and reporting infrastructure.
• Familiarity with synthesis, physical design, DFT, and power-aware timing analysis.
• Exposure to AI/ML-driven timing optimization and methodology development.
• Proven record of driving methodology improvements across multiple programs.

Education Requirements

Requires a Bachelor’s, Master’s, or PhD in Computer Science, Electrical/Electronics Engineering, VLSI, or a related engineering field. The posting lists degree-plus-experience alternatives (e.g., Bachelors + 4+ years; Masters + 3+ years; PhD + 2+ years) and also includes role-specific guidance of ~7+ years experience for this position.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.