Staff Engineer, STA and Synthesis

Job Title

Staff Engineer, STA and Synthesis

Role Summary

The STA Engineer leads timing closure and signoff readiness for block- and full-chip designs. This role develops and validates timing constraints, performs detailed timing and variation-aware analysis, debugs violations, and drives ECO-based timing optimizations in collaboration with Synthesis, CTS, Physical Design, and RTL teams.

Experience Level

Senior — 7–10 years of experience in Static Timing Analysis and timing closure.

Responsibilities

Key responsibilities include:

• Perform block- and full-chip STA across all modes and corners (pre-layout and post-layout).
• Analyze and debug setup, hold, recovery/removal, clock gating, and signal-integrity timing issues.
• Develop, validate, and maintain timing constraints (SDC) and timing exceptions.
• Drive timing closure via ECOs and timing optimizations with PD, Synthesis, CTS, and design teams.
• Perform variation-aware analysis for process, voltage, and temperature impacts and prepare signoff artifacts.
• Generate timing reports, participate in cross-functional reviews, and communicate closure status to stakeholders.

Requirements

Must-have technical skills and experience:

• Strong practical knowledge of timing concepts, CMOS fundamentals, and the semiconductor design flow.
• Hands-on experience with setup/hold analysis, path-based analysis, OCV/AOCV/POCV, derates, and MMMC concepts.
• Solid understanding of clock tree, clock uncertainty, latency, skew, and jitter.
• Experience developing and debugging timing constraints: SDC, false paths, multicycle paths, and case analysis.
• Experience with industry STA tools such as Synopsys PrimeTime or Cadence Tempus.
• Scripting proficiency in Tcl, Perl, or Python for automation and analysis.
• Proven ability to analyze and resolve timing violations independently and drive closure to signoff.

Nice-to-have:

• Exposure to low-power timing (UPF/CPF-aware STA), SI-aware timing, crosstalk, and IR-drop-aware timing closure.
• Experience with advanced technology nodes, variation-aware signoff methodologies, and flow automation.

Education Requirements

Not specified.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.