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Staff Engineer, RTL Implementation

Tenstorrent
July 29, 2026
Full-time
Remote friendly (Santa Clara, California, United States)
Worldwide
$100,000 - $500,000 USD yearly
Physical Design Jobs, Level - Senior

Job Title

Staff Engineer, RTL Implementation

Role Summary

Join the CPU design team to perform RTL implementation and physical design work for high-performance RISC-V CPU cores. The role focuses on synthesis, place-and-route, and PPA optimization across multiple process technologies and requires close collaboration with micro-architecture, verification, performance, and physical design teams.

This is a hybrid role based out of Austin, TX or Santa Clara, CA, working on end-to-end CPU implementation tasks from RTL through timing and power convergence.

Experience Level

Senior-level (Staff Engineer). The posting welcomes a range of seniorities and candidates will be assessed for the appropriate level during interview, but the title indicates a senior role.

Responsibilities

Primary responsibilities include delivering RTL implementation and driving physical-design experiments to improve power, performance, and area.

  • Perform synthesis and initial place-and-route for new and legacy CPU designs.
  • Iterate front-end CAD flows across multiple process technologies to improve results.
  • Collaborate with core micro-architects to refine core configurations for optimal PPA.
  • Design and run physical-design experiments; analyze and evaluate timing, power, and area outcomes.
  • Enhance and maintain physical-design environments, flows, and automation to improve development efficiency.
  • Work closely with RTL, verification (DV), performance, and PD teams to converge designs.

Requirements

Must-have skills and constraints for successful candidates.

  • Proven experience in high-performance physical design and RTL implementation.
  • Proficient in RTL coding (Verilog and/or VHDL) and familiar with simulation and power-analysis tools.
  • Experience with synthesis, place-and-route tools, flows, and physical-design methodology.
  • Solid background in CPU microarchitecture and performance optimization.
  • Track record of improving PPA through experiments and tooling enhancements.
  • Strong collaboration skills across architecture, verification, and PD teams.
  • Employment contingent on eligibility to access U.S. export-controlled technology (may require U.S. citizenship, permanent residency, or an export license).

Nice-to-have:

  • Experience with RISC-V CPU designs and integrating open-source toolchains with industry-standard flows.
  • Experience across multiple process nodes and familiarity with power-optimization methodologies.

Education Requirements

Not specified.


About the Company

Company: Tenstorrent

Headquarters: Austin, Texas, United States

Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.

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Date Posted: 2026-07-22