Staff Engineer, RTL Design

Job Title

Staff Engineer, RTL Design

Role Summary

Lead RTL design and verification efforts within the Memory Solutions Lab (MSL) Datacenter Device Solutions group, focusing on memory, storage, and data-center system features. Work with hardware and software architects to develop RTL IP, FPGA prototypes, lab bring-up, and validation for cloud and data center applications.

Work is research-and-development oriented and involves prototype development, feasibility studies, and collaboration across hardware, software, and test teams.

Experience Level

Senior level. Experience guidance: typically a BS with ~10 years, MS with ~8 years, or PhD with 5+ years of relevant RTL/ASIC/FPGA development experience.

Responsibilities

Core responsibilities include RTL microarchitecture, IP development, prototype validation, and cross-functional collaboration.

• Design and verify microarchitecture and RTL for high-performance IP and PoCs.
• Develop simulation testbenches, perform synthesis and timing analysis, and debug RTL using CAD tools.
• Lead lab bring-up, hardware validation, and system-level testing of RTL/IP on prototype boards and servers.
• Research and specify next-generation memory, storage controller, and interface features; evaluate emerging standards.
• Collaborate with hardware and software architects to build FPGA prototypes and perform feasibility studies.
• Support software integration and device driver debug on Linux/Windows as needed.
• Contribute to technical publications and patent filings where applicable.
• Perform other assigned duties to meet project objectives and timelines.

Requirements

Combination of technical skills, hands-on experience, and teamwork/communication abilities.

• Must-have:
  • Extensive RTL/HDL development experience, strong Verilog coding and integration skills.
  • Proven experience with RTL verification, simulation, testbench creation, integration, and debug using industry CAD tools (Synopsys, Mentor, Cadence, or equivalent).
  • Experience with synthesis, timing analysis, and design-for-test flows.
  • Hands-on hardware board bring-up and server/system integration experience.
  • Demonstrated ability to work across cross-functional teams and meet aggressive project deadlines; strong verbal and written communication.
• Nice-to-have:
  • Familiarity with FPGA design flows, partitioning, FPGA programming, and FPGA-specific timing/debug.
  • Experience or exposure to high-speed interfaces and protocols such as PCIe, CXL, NVMe, AXI, DDR4/DDR5, and Ethernet.
  • Experience developing or debugging device drivers on Linux/Windows.
  • Prior work publishing papers or filing patents in relevant fields.

Education Requirements

Preferred: Bachelor of Science with ~10 years of RTL development experience, Master of Science with ~8 years, or Ph.D. with 5+ years in Computer Engineering, Electrical Engineering, or a closely related technical field. (These degree-and-experience combinations are listed as preferred in the source.)

About the Company

Company: Samsung Semiconductor

Headquarters: San Diego, California, United States

Samsung Semiconductor is a global leader in semiconductor technology, providing innovative solutions for diverse applications including smartphones, electric vehicles, and data centers. As part of Samsung's Advanced Institute of Technology, the company focuses on cutting-edge research in areas such as CPU microarchitecture, AI, and HPC, fostering a diverse and inclusive work environment for its employees to thrive and innovate.