Staff Engineer – R&D Engineering

Job Title

Staff Engineer 6 R&D Engineering

Role Summary

Senior RTL and SoC integration engineer responsible for designing production-quality RTL, integrating IP blocks into subsystems, writing synthesis constraints, and resolving lint/CDC/synthesis issues to enable production silicon. Works across architecture, verification, and physical design teams and mentors junior engineers.

Experience Level

Senior level. Hiring guidance: typically expected to have 5+ years of relevant RTL/SoC experience (role expects engineers who have delivered RTL into silicon and owned blocks through synthesis and handoff).

Responsibilities

Primary responsibilities include front-end RTL design, integration, and ensuring designs meet timing and structural quality before handoff.

• Design and develop production RTL using Verilog/SystemVerilog for complex SoC/ASIC blocks.
• Integrate IP at the SoC/subsystem level and implement glue logic and interfaces.
• Write SDC for synthesis and ensure constraints reflect real timing intent.
• Run and debug lint, CDC, and synthesis checks; resolve issues early in the design cycle.
• Collaborate with verification, physical design, and architecture teams to close functional and structural issues.
• Contribute to microarchitecture discussions and translate intent into implementable RTL that meets performance, power, and area targets.
• Mentor and guide junior engineers on RTL quality, coding standards, and front-end best practices.

Requirements

Must-have technical skills and experience to perform the role.

• Hands-on RTL design experience and SoC/ASIC integration with a track record of owning blocks through synthesis and handoff.
• Strong proficiency in Verilog and SystemVerilog for production RTL development.
• Solid understanding of digital design fundamentals, microarchitecture, and multi-clock SoC integration challenges.
• Experience running and interpreting lint, CDC, and synthesis flows and tools (examples: SpyGlass, Leda, Fusion Compiler, Encounter) and debugging reported issues.
• Ability to write SDC and debug synthesis timing issues in complex designs.
• Clear communication skills across disciplines and demonstrated ownership of deliverables.
• Familiarity with using AI coding/assistant tools as part of the design workflow.

Nice-to-have:

• Experience with high-speed interfaces such as PCIe, USB, AXI, I2C, or JTAG.
• Familiarity with low-power design techniques.
• Scripting experience in Python, Tcl, or Perl.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or a related field is specified in the posting. The position cites a Bachelor's with a minimum of 5 years' related experience, or a Master's with 3 years' related experience. Equivalent practical experience is implied as an alternative.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.