Staff Engineer, Physical Design (SoC Engineering)

Job Title

Staff Engineer, Physical Design (SoC Engineering)

Role Summary

Senior physical design engineer responsible for RTL-to-GDSII implementation and sign-off of high-performance UCIe IP blocks on advanced process nodes. The role sits on a SoC/IP engineering team focused on meeting aggressive timing, power, and signal-integrity targets for die-to-die interfaces.

Primary mission: deliver tape-out-ready physical designs, develop robust automation, and solve complex die-to-die floorplanning, timing, power, and SI issues.

Experience Level

Senior — the posting specifies 3 to 10+ years of hands-on ASIC physical design experience and ownership of RTL-to-GDSII flows; title indicates a senior/staff level role.

Responsibilities

The engineer will own physical implementation and verification tasks for advanced-node IP, including automation and tape-out delivery.

• Lead RTL-to-GDSII implementation for UCIe and other die-to-die IP: synthesis, floorplanning, power grid architecture, placement, CTS, routing, and sign-off at 7nm/5nm/3nm.
• Close timing across multiple PVT corners and operating modes; optimize for latency, bandwidth, and power trade-offs in chiplet interfaces.
• Perform physical and electrical verification using IC Validator; resolve DRC, LVS, ERC, EM, IR-drop, and signal-integrity issues.
• Define and validate bump and pad-ring patterns and coordinate constraints with package teams.
• Develop and maintain automation scripts to streamline back-end flows and reduce cycle time.
• Prepare tape-out deliverables: GDSII databases, foundry checklists, and sign-off documentation.

Requirements

Must-have technical skills and experience; concise list of core expectations.

• 3 to 10+ years of hands-on ASIC physical design experience with demonstrated RTL-to-GDSII ownership and tape-out involvement on advanced nodes.
• Deep expertise with die-to-die interfaces (UCIe, HBM, high-speed DDR) and related timing, power, and SI challenges.
• Proficiency with Synopsys physical design and sign-off tools (IC Compiler II or Fusion Compiler, PrimeTime, IC Validator).
• Advanced scripting skills in Tcl and Python (Shell/Perl experience valuable) and experience automating back-end flows.
• Strong problem-solving skills for debugging timing, power delivery, and signal-integrity issues across corners.
• Nice-to-have: prior experience designing bump/pad rings and close collaboration with package teams; multiple advanced-node tape-outs.

Education Requirements

Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field (degrees explicitly listed in the posting).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.