Staff Engineer, Physical Design/Implementation
QualcommJob Title
Staff Engineer, Physical Design/Implementation
Role Summary
Lead and drive physical design implementation for complex, large-scale retimer-class and full-reticle ASIC products in advanced process nodes. Provide technical leadership to translate requirements, coordinate cross-functional teams, and deliver silicon that meets power, performance, area, and tapeout targets.
Experience Level
Senior-level. Typically expected to have multiple years of hands-on ASIC physical design experience; see Education Requirements for formal degree/year guidance.
Responsibilities
Core responsibilities include end-to-end physical implementation, timing and power closure, verification, and cross-team coordination to achieve tapeout-ready silicon.
- Lead end-to-end physical design flow: floorplanning, clock tree synthesis (CTS), placement & routing, power delivery network (PDN), timing analysis and closure.
- Plan and implement full-chip or hierarchical/full-reticle-scale SoC and retimer designs.
- Drive timing closure across all corners and modes (MMMC) with SI-aware optimizations.
- Perform and review physical verification checks (DRC, LVS) and DFM/DFY reviews.
- Integrate high-speed SerDes macros and mixed-signal IP, ensuring robust floorplan and signal integrity alignment.
- Drive IR/EM closure, power optimization, and congestion mitigation for large die designs.
- Collaborate with front-end, analog/SerDes, DFT, packaging, and silicon validation teams to achieve design convergence and tapeout readiness.
- Provide schedules, risk assessment, execution tracking, and technical input in design reviews; improve methodologies and flows.
Requirements
Required technical skills and experience. Degree requirements are listed in Education Requirements below.
- Proven experience with end-to-end ASIC physical design flow (floorplan, CTS, P&R, PDN).
- Expertise in timing closure and signoff methodologies, including multi-mode multi-corner (MMMC) strategies.
- Experience with physical verification flows (DRC, LVS) and DFM/DFY practices.
- Hands-on experience with industry-standard EDA tools (for example, Cadence Innovus or Synopsys ICC2).
- Solid understanding of power delivery and reliability (IR/EM) and clocking architectures.
- Experience addressing large-scale SoC integration challenges and tapeout execution.
- Proven ability to lead complex PD execution and coordinate cross-functional teams under tapeout pressure.
Nice-to-have:
- Experience with high-speed SerDes / retimer designs (PAM4-class signaling).
- Experience with full-reticle or near-reticle SoC implementation and advanced packaging (multi-die / chiplet).
- Background in data center, networking, or optical connectivity ASICs.
- Strong scripting and automation skills (Python, Tcl).
Education Requirements
One of the following is expected: Master's degree in Electrical Engineering, Computer Engineering, Computer Science, Science, Engineering, or a related field plus 3+ years of relevant ASIC design experience; OR Bachelor's degree in Science/Engineering or related field plus 4+ years of relevant ASIC design experience; OR PhD in Science/Engineering or related field plus 2+ years of relevant ASIC design experience.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
