Staff Engineer, Physical Design - High-Speed Interconnects

Job Title

Staff Engineer, Physical Design - High-Speed Interconnects

Role Summary

Staff Physical Design Engineer responsible for end-to-end implementation of high-bandwidth Network-on-Chip (NoC) and Uncore subsystems. The role spans architecture, RTL and physical implementation to drive Power, Performance and Area (PPA) outcomes for advanced process nodes.

You will collaborate with RTL, architecture and mid-level PD engineers to define floorplans, resolve interconnect challenges, and deliver scalable high-frequency IP.

Experience Level

Senior - typically 7+ years of hands-on physical design experience, with experience closing complex blocks or subsystems on FinFET nodes (7nm and below).

Responsibilities

Execute full physical design flow and partner with cross-functional teams to meet PPA and timing targets.

• Perform RTL-to-GDSII implementation for complex NoC and Uncore subsystems, ensuring timing closure and routability.
• Partner with RTL and Architecture teams for early feasibility analysis and recommend RTL or floorplan changes to meet PPA targets.
• Define hierarchical floorplanning, macro placement, pin assignments and global routing strategies for large die areas.
• Address interconnect challenges such as long-wire RC compensation, repeater strategies, and complex clock/reset distribution.
• Develop and refine automated hierarchical implementation flows and improve scripts/tools across technology nodes.
• Provide technical mentorship, lead design reviews, and establish best practices for high-performance physical implementation.

Requirements

Core qualifications and technical skills required for success in this role.

• 7+ years of physical design experience with a proven record of closing complex blocks or subsystems on FinFET nodes (7nm and below).
• Systems-level understanding of NoC designs and the ability to map RTL structures to physical layout.
• Proven experience with hierarchical P&R, top-level integration, budgeting and timing closure.
• Expert-level proficiency with Synopsys and/or Cadence implementation and sign-off tools.
• Data-driven approach to PPA tradeoffs, strong analytical rigor, attention to detail, and clear communication skills.
• Ability to operate at the intersection of architecture, RTL and physical implementation.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, or a related field.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.