Staff Engineer IP Verification - Digital Design Verification

Job Title

Staff Engineer, IP Verification - Digital Design Verification

Role Summary

Lead end-to-end block-level RTL verification for complex DRAM IP and subsystems (DDR5/LPDDR5/DDR6/LPDDR6) including low-power and power-management features. Own verification strategy, testbench development, regressions, coverage closure, and readiness for tapeout while collaborating with geographically distributed design and verification teams.

Experience Level

Senior / Staff level. Expected to provide technical leadership, mentor junior engineers, and influence verification methodology. Typically 7+ years of industry experience.

Responsibilities

Primary responsibilities include planning and executing comprehensive verification for block and subsystem RTL and delivering verified designs to tapeout readiness.

• Define verification scope, strategy, and plans for block/chip RTL verification.
• Develop, execute, and maintain SystemVerilog/UVM testbenches, test vectors, and regression suites.
• Run directed and constrained-random tests; analyze failures and triage root causes.
• Close functional and code coverage metrics; identify verification holes and drive remediation.
• Simulate, analyze, and debug RTL, testbench, and environment issues; coordinate fixes with design engineers.
• Provide verification status, risk assessments, and summaries to stakeholders; drive action closure.
• Collaborate internationally to develop new verification flows for DRAM and emerging memory designs.
• Mentor and lead verification teams; define verification roadmaps and methodological improvements.

Requirements

Must-have technical skills and experience for immediate contribution.

• Proven experience leading verification for complex IPs and subsystems.
• Hands-on SystemVerilog and UVM experience building block-level verification environments.
• Experience with constrained-random verification, regressions, and coverage-driven verification.
• Strong RTL debugging skills and experience resolving RTL/testbench/environment interactions.
• Familiarity with simulation and debug tools such as Virtuoso, Xcelium, SimVision, Verdi/Verisium (or equivalents).
• Scripting skills (Perl, Python) for testbench automation and regression management.
• Previous experience in DRAM or memory-related design and verification.
• Good communication skills and ability to work in multidisciplinary, geographically distributed teams.
• Proactive use of approved AI tools to support verification workflows and scripting while retaining technical responsibility for decisions.

Nice-to-have:

• Experience with low-power/power-management verification techniques for high-speed memory interfaces.
• Familiarity with multiple DRAM architectures and features across DDR generations.

Education Requirements

Bachelor's degree (engineering) with ~7–9 years of related experience, or a postgraduate degree in Electronics Engineering or a related engineering field with ~6–8 years of related experience.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.