Staff Engineer, Physical Design

Job Title

Staff Engineer, Physical Design

Role Summary

Responsible for block-level physical design and methodology for next-generation high-performance processor ASICs in advanced CMOS nodes. Work with a global team to maintain and improve place-and-route flows and enable robust tapeout for server, 5G/6G and networking applications.

Role is hands-on: implementation, timing closure, ECO delivery and close collaboration with RTL and timing teams.

Experience Level

Senior — typically requires 5+ years of physical-design experience, including work at advanced process nodes (e.g., 7nm, 5nm or below).

Responsibilities

Primary responsibilities delivering block-level physical design and supporting methodology.

• Maintain, enhance and support place-and-route flows using industry-standard EDA tools.
• Perform synthesis, placement, routing, timing analysis and timing closure for intermediate and complex logic blocks.
• Develop and implement timing and logic ECOs to resolve congestion and timing issues.
• Collaborate with RTL designers to drive necessary design modifications.
• Debug and resolve block-level timing issues at the partition level and with the global timing team.
• Support physical verification and signoff processes.
• Create and maintain automation scripts to improve flow efficiency.

Requirements

Must-have technical skills and experience; nice-to-have items noted.

• 5+ years of physical-design experience focused on block-level place-and-route for advanced CMOS nodes (7nm, 5nm, or below).
• Proficient with physical-design EDA: Cadence Genus and Innovus; Synopsys IC Compiler and Fusion Compiler.
• Expertise in static timing analysis tools such as Tempus or PrimeTime.
• Experience with EM/IR and crosstalk analysis tools (Voltus or PrimeRail).
• Proficient scripting ability (Tcl, Perl, Makefile) to automate design processes.
• Strong debugging skills, attention to detail, effective communication, and teamwork.
• Nice to have: working knowledge of physical verification and formal tools (Calibre, LEC, Formality).

Education Requirements

Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.