Staff Engineer, Physical Design - Cores
SiFiveJob Title
Staff Engineer, Physical Design - Cores
Role Summary
The Staff Physical Design Engineer will own RTL-to-GDSII physical implementation of high-performance CPU core blocks. You will deliver high-frequency, power-efficient core designs and collaborate closely with architecture, RTL, and power teams to optimize Power, Performance, and Area (PPA).
This role sits on the cores team in Bengaluru and focuses on block-level implementation, timing closure, CTS, congestion management, and methodology improvements.
Experience Level
Senior — requires 7+ years of hands-on experience in physical design implementation, including block-level tape-outs for high-speed digital logic such as CPUs.
Responsibilities
Primary responsibilities include implementation, optimization, and cross-team collaboration for CPU core blocks.
- Lead physical implementation for high-frequency CPU core blocks: synthesis, place & route, and signoff.
- Collaborate with Architecture, RTL, and Power teams to co-design and meet aggressive PPA targets.
- Identify logic-depth bottlenecks and recommend RTL/pipelining or structural changes to improve timing.
- Resolve core-specific issues: timing closure, datapath placement, routing congestion, and complex CTS.
- Optimize block-level implementations for frequency, power, and area trade-offs across product lines.
- Develop and improve physical design flows, automation scripts, and methodologies for complex core implementation.
Requirements
Must-have technical skills and constraints for the role.
- 7+ years of hands-on physical design implementation experience with proven block-level tape-outs for high-speed digital logic (CPUs).
- Deep CPU/datapath experience: implementation of control logic, execution units (ALUs, FPUs), or custom datapaths and familiarity with high-frequency design challenges.
- Ability to read and interpret RTL and collaborate across abstraction layers (architecture, RTL, power).
- Proven problem-solving skills for aggressive PPA targets using industry-standard physical design techniques.
- Hands-on experience with Synopsys and/or Cadence RTL-to-GDSII implementation and sign-off toolflows.
- Willingness and ability to undergo background/reference checks and to provide proof of right to work in India.
- Ability to obtain export-control authorization or for the company to obtain necessary export licenses if required.
Education Requirements
Bachelor's or Master’s degree in Electrical Engineering or Computer Engineering is required (as stated). No certifications or equivalent-experience language was specified beyond the degree requirement.
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
