Staff Engineer, Physical Design

Job Title

Staff Engineer, Physical Design

Role Summary

Staff Physical Design Engineer responsible for physical implementation, timing closure, and global signal and clock distribution for advanced-node ASICs. You will work with RTL, architecture, circuit, and signoff teams to translate complex designs into high-performance silicon.

This role focuses on clocking architectures, long-wire interconnect planning, and circuit-level timing/noise integrity to meet Power, Performance, and Area (PPA) targets.

Experience Level

Senior — typically 8+ years of hands-on physical design experience, including successful tape-outs on advanced process nodes (7nm and below preferred).

Responsibilities

Core responsibilities include:

• Architect and implement low-skew, high-performance clock distribution (mesh, H-tree, hybrid); optimize clock buffers, gating, and multi-source CTS.
• Plan and manage global interconnect routing, long-wire span limits, repeater strategies, and mitigation of RC delay and routing congestion.
• Diagnose and resolve circuit-level timing and noise issues including crosstalk, electromigration (EM), and dynamic IR-drop on global nets.
• Perform MCMM timing closure and jitter analysis to achieve robust signoff across corners and modes.
• Collaborate with RTL and architecture teams to identify structural bottlenecks and propose microarchitectural or circuit-level optimizations.
• Provide technical leadership and mentor junior engineers; own signoff criteria and contribute to advanced design methodologies and flows.

Requirements

Must-have qualifications and skills:

• 8+ years of hands-on physical design experience with tape-outs on advanced process nodes (7nm and below preferred).
• Deep expertise in physical clocking structures, global interconnect routing, MCMM timing closure, and jitter analysis.
• Strong fundamentals in CMOS circuit behavior, RC interconnect modeling, and transistor-level timing/noise concepts.
• Expert-level experience with industry EDA tools (Synopsys Fusion Compiler/PrimeTime and/or Cadence Innovus/Tempus), including CTS, parasitic extraction, and STA engines.
• Proven ability to debug complex timing violations, crosstalk delay, routing congestion, and transient IR-drop with minimal supervision.
• Authorization to work in India and ability to pass background and export-control checks.

Nice-to-have:

• Experience influencing microarchitecture from a physical-design perspective and prior mentoring or technical leadership roles.
• Experience across a range of product types from edge devices to high-performance platforms.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.