Staff Engineer - Physical Design
SiFiveJob Title
Staff Engineer - Physical Design
Role Summary
Work as a senior physical design engineer responsible for translating complex RTL into high-performance silicon through end-to-end physical implementation. The role partners closely with RTL and architecture teams and drives PPA (power, performance, area) improvements across diverse IP blocks.
Experience Level
Senior — expects 7+ years of hands-on physical design experience; proven track record of tape-outs on advanced process nodes.
Responsibilities
Deliver full physical implementation and provide technical leadership across product lines.
- Drive end-to-end physical design flow: synthesis, floorplanning, place & route, and signoff for major subsystems and IP blocks.
- Collaborate with RTL and architecture teams from early design through signoff to identify and remove physical bottlenecks.
- Analyze and resolve timing closure, routing congestion, IR drop, and power-density issues; co-design microarchitectural and structural fixes.
- Apply advanced physical design techniques tailored to different design classes (low-power edge IP, automotive-reliability designs, high-bandwidth fabrics).
- Contribute to methodology, automation, and implementation flows; improve team practices and tools.
- Mentor junior engineers and act as a subject-matter expert for complex implementation challenges.
Requirements
Must-have technical skills and experience for immediate contribution.
- Must: 7+ years of hands-on physical design experience with successful tape-outs; experience on advanced nodes (7nm and below preferred).
- Must: Deep experience implementing at least one major IP domain (CPU, high-speed interconnect/fabrics, cache/memory hierarchies, or accelerators) and ability to adapt to new logic classes.
- Must: Strong co-design mindset: understand how physical choices affect microarchitecture and be able to drive cross-functional design changes.
- Must: Expert proficiency with industry EDA tools — Synopsys (Fusion Compiler, PrimeTime) and/or Cadence (Innovus, Tempus) for implementation and sign-off.
- Must: Advanced problem-solving skills to debug structural timing violations, routing congestion, dynamic IR drop, and other complex issues with minimal supervision.
- Nice-to-have: Experience addressing automotive reliability requirements or other high-reliability standards and extreme low-power optimization.
- Note: Candidates must be able to pass background/reference checks and demonstrate the right to work in India; export-control authorization or ability to obtain required licenses may be required.
Education Requirements
Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related field (as stated). No alternative equivalent-experience language was provided.
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
