Staff Engineer, Memory Layout

Job Title

Staff Engineer, Memory Layout

Role Summary

Technical lead responsible for architecting layout automation, verification, and methodology for embedded memory compilers (SRAM/ROM/register files). You will define layout guidelines, build production-grade automation, and integrate verification and extraction flows to scale memory IP across advanced process nodes.

Position sits on the Memory Layout Methodology and Automation team in Noida and provides technical leadership to memory compiler and layout development teams, and collaborates with foundries and EDA vendors.

Experience Level

Senior - 8+ years of experience in custom IC layout methodology, EDA automation, or physical design enablement.

Responsibilities

Lead design and delivery of layout methodology, automation frameworks, and automated verification flows for embedded memory IP:

• Lead technology studies and process entitlement evaluations for advanced nodes (FinFET, GAA) to define feasible layout approaches.
• Architect and implement production-grade layout automation frameworks using Python and TCL for large-scale memory IP generation and verification.
• Develop and maintain automated physical verification flows integrating tools such as Synopsys Custom Compiler, StarRC, and Ansys Totem for extraction and EM/IR analysis.
• Author implementation design rules, best practices, and layout methodologies for SRAM, ROM, and register file compilers.
• Evaluate and integrate next-generation EDA tools with internal flows and vendor collaborations.
• Provide technical leadership and mentor layout development teams; diagnose complex verification failures and tool-integration issues.
• Collaborate with foundry partners on design-technology co-optimization and feed layout constraints back into process discussions.

Requirements

Key qualifications and skills required to perform the role. Must-haves are listed first; nice-to-haves follow.

• Must-have: 8+ years of hands-on experience in custom IC layout methodology, EDA automation, or physical design enablement with a focus on embedded memory architectures (SRAM, ROM, register files).
• Must-have: Deep proficiency in Python and TCL for building production-grade automation and verification infrastructure.
• Must-have: Extensive experience developing and deploying automated physical verification flows using Synopsys Custom Compiler, StarRC, Ansys Totem, or equivalent tools.
• Must-have: Strong understanding of advanced process nodes (FinFET, GAA, 5nm and below) and translating foundry design rules into automation and guidelines.
• Must-have: Working knowledge of DRC/LVS/antenna checking, parasitic extraction, and EM/IR analysis in full-custom layout contexts.
• Must-have: Demonstrated ability to lead technical projects, mentor engineers, and produce maintainable automation used by teams at scale.
• Nice-to-have: Experience collaborating directly with foundry teams on co-optimization or familiarity with AI/ML frameworks for automating engineering tasks.

Education Requirements

Bachelor's, Master's, or Ph.D. in Electrical Engineering, Electronics Engineering, Computer Science, or a related technical field with focus on EDA or layout methodology.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.