Staff Engineer - HBM Layout

Job Title

Staff Engineer - HBM Layout

Role Summary

Layout Design engineer on the High Bandwidth Memory (HBM) team responsible for block- and full-chip layout for HBM products targeting AI and high-performance computing applications.

Works across global teams on reticle development, tapeout support, physical verification and integration with advanced packaging requirements.

Experience Level

Senior-level role; typically requires 8–15 years of experience in analog/custom layout design across advanced CMOS process nodes (planar, FinFET).

Responsibilities

Main responsibilities include block implementation, verification, and coordination for multi-project tapeouts.

• Design and develop critical mixed-signal and custom-digital block layouts; support full-chip integration.
• Develop and build PWF reticles and support tapeout activities.
• Collaborate with scribe design and advanced packaging teams to capture packaging requirements and reviews.
• Engage on TSV-related electrical, thermal and mechanical design considerations with cross-functional teams.
• Create and maintain DFMEA related to advanced packaging process steps such as PWF and die stacking.
• Perform layout verification (LVS/DRC/antenna), quality checks and documentation.
• Plan, estimate, schedule and execute multiple layout projects to meet milestones and delivery targets.
• Mentor and guide junior layout engineers and review sub-block layouts.
• Communicate effectively with global engineering teams to ensure layout project success.

Requirements

Must-have technical skills and proven experience for successful execution in this role.

• Must-have: Expertise in Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS.
• Must-have: Hands-on experience creating layouts for critical analog/mixed-signal blocks (e.g., PLL, ADC, DAC, LDO, bandgap, reference generators, charge pumps, current mirrors, comparators, differential amplifiers, temperature sensors).
• Must-have: Experience with reticle development and full-chip verification.
• Must-have: Strong understanding of layout fundamentals (matching, electromigration, latch-up, coupling/crosstalk, IR-drop, parasitics) and how layout affects speed, capacitance, power and area.
• Must-have: Strong skills in physical verification and problem solving for custom layouts.
• Must-have: Ability to automate layout tasks and leverage AI features to improve productivity.
• Must-have: Experience managing multiple layout projects and ensuring quality controls across stages.
• Must-have: Excellent verbal and written communication skills and demonstrated leadership in planning and execution.
• Nice-to-have: Multiple tapeout support experience; prior work with TSV design, scribe design interactions, and DFMEA creation for advanced packaging.

Education Requirements

BE (Bachelor of Engineering) or MTech in Electronics/VLSI Engineering.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.