Staff Engineer, Formal (IOMMU-N)

Job Title

Staff Engineer, Formal (IOMMU-N)

Role Summary

Lead formal verification efforts for RISC-V processors and associated IP implemented in Chisel. You will create and execute formal verification plans, write and debug assertions, use formal tools to prove correctness, and collaborate with design teams to close corner-case bugs and improve verification flows.

This role is based in Bengaluru. Employment is contingent on background checks, proof of right to work in India, and any required export-control approvals.

Experience Level

Senior - 7+ years of hands-on experience in formal verification of digital hardware designs.

Responsibilities

Primary responsibilities include:

• Develop and implement formal verification plans for complex digital designs (RISC-V processors and related IP).
• Write, debug, and maintain formal properties (assertions and assumptions) in Chisel/Scala to specify design behavior and catch corner cases.
• Use formal verification tools and flows to prove correctness and uncover potential issues.
• Collaborate with design engineers to review architectures, clarify specifications, and resolve formal failures.
• Create verification environments and automation using Chisel, Scala, and TCL scripting.
• Improve formal verification efficiency and coverage, including adapting constrained-random and coverage strategies to Chisel-based flows.
• Analyze formal results, debug failures, and drive issue resolution with the design team.
• Contribute to continuous improvement of formal verification flows and methodologies.

Requirements

Must-have qualifications:

• 7+ years of hands-on formal verification experience on digital hardware designs.
• Proficiency in Scala and practical experience with the Chisel hardware description language.
• Strong understanding of formal verification methodologies (assertion-based verification, model checking, equivalence checking).
• Experience writing effective formal properties and assertions.
• Familiarity with commercial or open-source formal verification tools and their application to complex designs.
• Experience with TCL scripting for tool automation and flow development.
• Solid knowledge of digital design principles, computer architecture, and FPGA/ASIC design flows.
• Strong problem-solving skills and effective communication and collaboration abilities.

Nice-to-have:

• Experience adapting constrained-random or UVM-like methodologies for Chisel-based verification or experience with chisel-formal or similar frameworks.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.