Staff Engineer - DV
Work as a senior design verification engineer on high-performance CPU verification for RISC-V processors. You will develop SystemVerilog/UVM testbenches, write targeted tests, and drive coverage closure in collaboration with design and architecture teams.
Senior β suggested 7β12 years of verification experience.
Primary responsibilities involve verification development, test generation, and integration to validate CPU functionality and coverage.
Must-have technical skills and experience for the role.
Bachelor's or Master's degree in Engineering (e.g., Electrical/Computer Engineering) as stated in the posting.
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
