Staff Engineer - DV
Senior design verification engineer on the CPU verification team responsible for SystemVerilog/UVM test development for high-performance RISC-V CPUs. Work includes writing targeted tests, using internal test generators, implementing test plans, and integrating third‑party verification IP.
This role is based in Bengaluru and requires authorization to work in India; offers are contingent on satisfactory background checks and export-control authorization where required.
Senior — typically 7–12 years of experience in design verification, preferably with CPU verification experience.
Primary responsibilities include developing verification tests, driving coverage closure, and integrating verification components.
Key technical skills and experience required or strongly preferred.
Bachelor's or Master's degree in Engineering (the posting specifies a Bachelor's or Master's in Engineering).
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
