Staff Engineer, Digital IC Design

Job Title

Staff Engineer, Digital IC Design

Role Summary

Design and verify digital ASIC blocks and subsystems for high-speed data-communication integrated circuits, with emphasis on PAM4 optical DSP and PHY transceivers. The role sits on the Connectivity BU engineering team focused on DSPs for cloud and AI data-center interconnects.

Primary mission: deliver RTL, verification, synthesis and timing-closure for high-performance PHY and DSP blocks and support post-silicon debug and correlation.

Experience Level

Mid-level — typically 3–5 years of relevant professional experience (2–3 years with a Master's/PhD).

Responsibilities

Core responsibilities include architecture, RTL implementation, verification, timing closure and silicon bring-up activities.

• Define ASIC specifications and micro-architecture for digital signal-processing and communications algorithms.
• Design RTL for PHY transceivers and DSP blocks supporting line rates from ~25Gbps to 224Gbps.
• Develop and validate DSP algorithms, analyze trade-offs (performance, power, area, complexity, design time) and produce optimization guidance.
• Implement and review RTL; perform lint, CDC analysis, synthesis, formal equivalence, static timing analysis and PPA analysis.
• Participate in functional and gate-level verification and debug; collaborate with verification and silicon teams for post-silicon debug and correlation.
• Work with cross-functional teams to ensure design-for-test and production readiness.

Requirements

Must-have technical skills and experience. Advanced degree listed separately under Education Requirements.

• Experience with high-speed DSP design, Forward Error Correction (FEC), and high-speed interfaces such as PCIe and UCIe.
• Proven ability to map DSP models to RTL and to integrate DSP blocks into ASIC flows (synthesis and timing closure).
• Strong hands-on skills in Matlab, Verilog, SystemVerilog; familiarity with scripting (Perl, Unix shell).
• End-to-end VLSI design experience: micro-architecture, RTL coding, synthesis and timing closure.
• Experience in RTL development at block and subsystem levels, and gate-level verification/debug.
• Understanding of Design-for-Test (DFT) concepts and ability to work in a fast-paced, changing environment.
• Strong communication and teamwork skills.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering or a related field with 3–5 years of relevant experience; or a Master's degree or PhD in Computer Science, Electrical Engineering or related fields with 2–3 years of experience. Equivalent practical experience will be considered.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.