Principal PCIe/CXL RTL Design Engineer

Job Title

Principal PCIe/CXL RTL Design Engineer

Role Summary

Lead RTL design and micro-architecture development for high-performance PCIe and CXL controllers/IP blocks in ASIC and SoC projects. Work on a cross-functional team with architects, verification, physical design, and firmware to deliver silicon-ready RTL and support bring-up.

Responsible for driving architecture-to-silicon implementation, resolving complex RTL/ timing/functional issues, and mentoring junior engineers.

Experience Level

Senior — Principal-level contributor. Typically requires ~10+ years of industry experience in digital design/RTL and PCIe/CXL-related projects.

Responsibilities

Primary responsibilities include system- and block-level RTL design, collaboration, and delivery:

• Design and implement RTL (SystemVerilog/Verilog) for PCIe and CXL protocol engines and datapaths.
• Define micro-architecture, create design specifications, and produce RTL that meets performance and area targets.
• Work with verification teams to develop / review testplans, support UVM/SV testbench development, and debug functional failures.
• Drive synthesis, timing-closure, and implementable RTL coding styles; collaborate with physical design for timing and power optimization.
• Perform FPGA prototyping and silicon bring-up support, including root-cause analysis and hardware/software debug.
• Mentor and review designs from less experienced engineers; lead design reviews and architecture discussions.
• Coordinate with system architects, firmware, and external IP vendors to ensure interoperability and compliance with PCIe/CXL specs.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

• Extensive RTL design experience in SystemVerilog or Verilog for high-speed interfaces.
• Deep experience with PCIe protocol (controller/endpoint/root complex) and CXL concepts and transactions.
• Proven track record delivering silicon or silicon-ready IP (synthesis, timing closure, tooling flows).
• Experience with verification methodologies (UVM, SystemVerilog) and debug tools.
• Hands-on experience with FPGA prototyping, logic analyzers, protocol analyzers, and lab bring-up.
• Proficiency with scripting (Python, Tcl, Perl or similar) and common EDA tool flows.
• Strong problem-solving, communication, and cross-team collaboration skills.

Nice-to-have:

• Experience with PCIe Gen4/Gen5/Gen6 and CXL 1.x/2.0 implementations.
• Prior experience as technical lead or architect of high-speed interface IP.

Education Requirements

Not specified.

About the Company

Company: Rambus

Headquarters: Sunnyvale, California, USA

Rambus is a global leader in advanced semiconductor and technology solutions, specializing in enhancing data access and improving performance in computing, networking, and storage applications. The company is known for its innovative IP and solutions in memory, security, and interface technologies. With a strong focus on research and development, Rambus continues to push the boundaries of technology to meet the growing demands of the digital age.