Staff Engineer, Digital Design Engineering

Job Title

Staff Engineer, Digital Design Engineering

Role Summary

Lead technical design and delivery for reusable digital IP within Analog Devices' Digital IP team. Provide architecture and hands-on RTL leadership, mentor engineers, and coordinate IP integration across product teams.

Focus areas include digital block architecture, RTL coding, IP packaging for integration, and establishing IP catalog and evaluation processes.

Experience Level

Senior — requires significant experience; posting specifies 12+ years of relevant experience.

Responsibilities

Primary duties include technical leadership, IP development, and cross-team coordination.

• Provide technical leadership and mentor digital design engineers across CDC, low-power, synthesis/timing closure, DFT, and silicon debug.
• Architect and implement digital blocks and accelerators in Verilog/SystemVerilog with PPA optimization.
• Design and maintain digital IP packaging for RTL, constraints, CDC/timing waivers, DFT artifacts, and integration sequences.
• Define and maintain a digital IP catalog and development flows to enable reuse across business units.
• Evaluate third-party IPs for PPA, integration ease, DFT/DV maturity and provide recommendations.
• Lead design reviews, enforce quality metrics, and establish benchmarking and evaluation flows.
• Collaborate with product teams and program managers to align schedules, milestones, and deliverables.
• Drive adoption of approved AI tools to improve efficiency and execution.
• Manage consolidation and curation of IP assets including standard peripherals, cores, and high-speed interfaces.
• Distill complex technical details into clear guidance to reduce ambiguity across teams.

Requirements

Must-have technical skills and experience for successful performance in this role.

• 12+ years of relevant experience in digital design, architecture, and RTL development (Verilog/SystemVerilog).
• Proven experience leading large, complex hardware projects and mentoring engineering teams.
• Deep understanding of ASIC/SoC product development including design verification, timing constraints/closure, and physical implementation; hands-on experience in several of these areas.
• Expertise in control-path and data-path digital design and correct-by-construction approaches.
• Experience specifying DV requirements (test plans, coverage metrics) and evaluating DV quality.
• Knowledge of linting, CDC, formal equivalence, DFT concepts, power analysis, and low-power design techniques.
• Experience developing timing constraints and performing synthesis and static timing analysis.
• Strong communication and interpersonal skills for coordinating with geographically distributed teams and stakeholders.
• Familiarity with standard on-chip interfaces (APB/AHB/AXI/Stream) and high-speed interfaces (DDR, PCIe, MIPI, etc.).
• Understanding of processor/SoC architectures and DSP fundamentals.
• Willingness to travel up to 10%.

Nice-to-have: experience with IP management tools (Methodics, Perforce, GitHub), prior work on processor subsystems (caches, interconnects, MMU, debug/trace), and experience evaluating third-party IP on integration and DV maturity.

Education Requirements

Minimum B.E. / B.Tech in Electrical, Electronics, or Computer Science (or equivalent degree) is specified.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.