Staff Engineer, Digital Design Engineering

Job Title

Staff Engineer, Digital Design Engineering

Role Summary

Design and maintain FPGA-based prototyping platforms to enable early software development, RTL validation and system integration for complex SoC/ASIC designs. Work within an international FPGA prototyping team and collaborate closely with digital design, firmware, and silicon validation engineers.

Own the end-to-end FPGA build flow — RTL ingestion, synthesis, implementation, timing closure, and delivery of validated FPGA images and debug infrastructure to software and validation teams.

Experience Level

Senior — requires significant experience; posting specifies 7+ years of FPGA design experience.

Responsibilities

Key responsibilities center on FPGA prototyping, build automation, and cross-team integration.

• Develop and maintain FPGA prototyping platforms on Xilinx UltraScale+ (VU19P) and proFPGA multi-FPGA systems.
• Own Vivado-based synthesis, implementation, incremental compile, and timing-closure flows.
• Port ASIC RTL to FPGA: adapt clock trees, replace memories, create IP stubs, and develop constraints.
• Automate build and file-management flows using TCL and Python for full and incremental Vivado builds.
• Debug synthesis/implementation failures, resolve timing violations, and optimize QoR (clock skew, utilization, routing congestion).
• Provide FPGA images and debug support to silicon validation and firmware teams; develop bare-metal test programs when required.
• Work with FPGA vendor tools and support channels to resolve tooling issues and file change requests.

Requirements

Must-have technical skills and experience:

• 7+ years of FPGA design experience focused on prototyping/implementation.
• Expert-level Vivado experience: synthesis, implementation, timing constraints, and incremental compile.
• Experience with ASIC-to-FPGA prototyping: RTL porting, memory model replacement, and clock adaptation.
• Deep understanding of FPGA clocking (MMCM, PLL, BUFG variants, clock muxing) and timing-closure on large designs (100K+ LUTs).
• Experience developing XDC constraints (clock definitions, false paths, multicycle paths, clock groups).
• Experience scripting/automation with TCL and Python; familiarity with SystemVerilog-based flows.
• Strong debugging skills for lab bring-up and synthesis/implementation failures.

Nice-to-have:

• Hardware lab experience: board bring-up, oscilloscope/logic-analyzer debug, JTAG probing, signal-integrity awareness.
• Embedded C / bare-metal firmware experience on ARM platforms and GCC toolchains.
• Familiarity with Intel/Quartus flows, ASIC simulation or synthesis tools (VCS, Xcelium, Synopsys DC), and bus protocols (AXI/AHB/APB).
• Experience with debug infrastructure (JTAG, CoreSight, ILA) and Git version control.

Education Requirements

BS/BE in Electrical Engineering, Computer Science, or Computer Engineering (with industry experience) is listed. MSc or PhD in Electrical Engineering, Computer Science, or a related field is also noted as acceptable.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.