Senior Design Verification Engineer

Job Title

Senior Design Verification Engineer

Role Summary

Design Verification Engineer on the Silicon Chassis team responsible for independently owning verification of interconnect and chassis IP blocks from planning through coverage closure. Work includes building reusable verification environments, driving coverage and quality signoff, and coordinating with architecture, design, and software teams.

Experience Level

Senior — typically requires 5+ years of relevant design verification experience.

Responsibilities

Primary responsibilities include end-to-end verification ownership, collaboration across disciplines, and improving verification infrastructure.

• Own verification planning and execution for assigned IP and subsystem features; drive test plans to coverage closure and quality signoff.
• Develop scalable, reusable verification environments, testbenches, checkers, constrained-random tests, and debug infrastructure.
• Collaborate with architecture, design, and software teams on spec reviews, feature clarification, bug triage, and resolution.
• Analyze simulation failures, perform root-cause analysis, and drive fixes to closure; own end-to-end debug for assigned blocks.
• Define and implement functional coverage models and lead coverage-closure activities.
• Improve verification automation, regression quality, and development efficiency.
• Mentor junior engineers on verification practices, debugging techniques, and code quality.

Requirements

Key technical must-haves and preferred skills for successful execution of the role.

• Must-have:
  • Strong proficiency in SystemVerilog and UVM methodology.
  • Practical experience verifying router, switch, crossbar, or NoC components (arbitration, flow control, switching fabric).
  • Understanding of credit-based flow control and VC-based deadlock avoidance.
  • Experience creating traffic generators and test workloads (uniform random, hotspot, adversarial, trace-driven) for interconnect verification.
  • Familiarity with mesh/ring/crossbar topologies and routing algorithms.
  • Experience writing SVA (SystemVerilog Assertions) for protocol compliance checking.
  • Experience building coverage models and driving test plans to closure.
  • Strong debugging skills with ability to trace transactions across multiple protocol domains.
• Nice-to-have:
  • Experience verifying QoS and bandwidth partitioning in fabric components.
  • Experience with AI-assisted verification workflows (LLM-assisted code review or generation).
  • Prior work on fabric or SoC interconnect IPs.

Education Requirements

B.Tech or M.Tech, or BS/MS in Electrical Engineering, Computer Science, or a related technical field. The posting specifies 5+ years of relevant design verification experience alongside these degrees.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.