Staff Engineer, Design Verification (VIP)

Job Title

Staff Engineer, Design Verification (VIP)

Role Summary

Senior verification engineer responsible for designing, developing, and maintaining Verification IP (VIP) for industry-standard protocols. The role is on an R&D engineering team building reusable, coverage-driven VIP used by semiconductor customers and IP teams.

Work includes creating verification architecture, writing sequences and checkers in SystemVerilog/UVM, debugging multi-layer protocol failures, and supporting customer integration and deployment.

Experience Level

Senior — typically 5+ years of hands-on Verification IP or related verification experience.

Responsibilities

Primary responsibilities include developing VIP, building verification plans, and supporting customer integrations.

• Design, develop, and maintain Verification IP using SystemVerilog and UVM for protocols such as AMBA, PCIe, USB, Ethernet, UEC, UAL, and MIPI.
• Create comprehensive verification plans mapping protocol specifications to test scenarios, coverage goals, and corner-case strategies.
• Implement sequences, tests, and checkers to enable coverage-driven verification across functional and code coverage.
• Debug complex simulation failures across multi-layer protocol stacks; identify root causes in VIP and customer integrations.
• Enhance VIP products for performance, reusability, and scalability as protocols and customer needs evolve.
• Support customers and field teams during VIP integration and deployment; troubleshoot and resolve integration issues.
• Collaborate with Design IP teams, R&D engineers, and application teams to align VIP capabilities with product roadmaps.

Requirements

Must-have technical skills, experience, and attributes for immediate contribution.

• 5+ years of hands-on Verification IP development or equivalent verification experience.
• Strong proficiency in SystemVerilog and UVM methodology for building reusable, scalable verification environments.
• NVMe protocol expertise is mandatory; PCIe experience is desirable.
• Deep working knowledge of at least two industry-standard protocols such as USB, Ethernet, or MIPI is preferred.
• Hands-on experience with BFMs, IP/VIP development, and integration.
• Proven ability to create and execute coverage-driven verification plans, including functional and code coverage analysis.
• Experience debugging complex simulation failures and resolving multi-layer integration issues.
• Ability to work directly with customers or field teams during product deployment is a strong plus.
• Strong problem-solving skills, good written and verbal communication, and the ability to work independently or in teams.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Computer Science, or a related technical field — or equivalent practical experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.