Staff Engineer, Design Verification (Verification IP)
SynopsysJob Title
Staff Engineer, Design Verification (Verification IP)
Role Summary
Design, develop, and maintain Verification IP (VIP) using SystemVerilog and UVM for industry protocols, and deliver coverage-driven verification solutions that scale across products and customers. The role works with R&D, Design IP teams, and field teams and includes customer deployment and support.
Experience Level
Senior - typically 5+ years of hands-on experience developing Verification IP or SystemVerilog/UVM-based test benches.
Responsibilities
Owner of verification IP features and verification plans from design through customer deployment.
- Design, implement, and maintain VIP using SystemVerilog and UVM for protocols such as DFI, DRAM, AMBA, PCIe, USB, and Ethernet.
- Create comprehensive verification plans mapping protocol specifications to testable scenarios, coverage goals, and corner-case strategies.
- Develop sequences, test scenarios, checkers, and scoreboards to drive functional and code coverage.
- Debug complex simulation failures across multi-layer protocol stacks and diagnose root causes in VIP logic and customer integrations.
- Improve VIP performance, reusability, and scalability as protocols and customer requirements evolve.
- Collaborate with Design IP, R&D, and field teams to align VIP capabilities with product roadmaps and customer needs.
- Support customers during VIP integration and deployment, troubleshooting issues and ensuring successful bring-up.
Requirements
Key skills and experience required and preferred for successful performance in this role.
- Must-have: 5+ years of hands-on experience developing Verification IP or building SystemVerilog/UVM-based test benches.
- Must-have: Deep working knowledge of at least two industry-standard protocols (examples: AMBA (AXI, AHB, APB), DFI, DRAM, PCIe, Ethernet).
- Must-have: Strong proficiency in SystemVerilog and UVM methodology for reusable, scalable verification environments.
- Must-have: Experience creating and executing coverage-driven verification plans, including functional and code coverage analysis.
- Must-have: Proven ability to debug complex simulation failures and resolve issues across protocol layers and integration boundaries.
Nice-to-have:
- Experience working directly with customers or field teams during product deployment.
- Prior work on VIP architecture, performance tuning, or expanding protocol support across product lines.
Education Requirements
Bachelor's or Master's degree in Electronics Engineering, Computer Science, or a closely related technical field - or equivalent practical experience.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
